Folks: A few questions:

      direction on first level (chip) joins - at present, >85%wt Pb is
      specified as exempt; I understand there are discussions in progress
      to reduce that threshold; if true, what are the specifics? I have
      also been told that, in joints involving both high-Pb material
      (chip-side) and eutectic (37%; carrier-side) lead solder, a
      computation may be made, aggregating the masses of the high and
      eutectic lead materials to figure an average joint composition,
      against which compliance with the limit would be assessed; is there
      official guidance that this would indeed be acceptable?

      chip joins: what is industry's take on becoming lead-free at this
      level? are there JEDEC changes in progress to address lead-free chip
      joints? who is most knowledgeable in this arena?

      can the (apparent) threshold limit of 0.1% be applied to products
      with lead in solder, some of which was initially 37%, presuming the
      volume is very small? would the threshold limit be applied at the
      packaging substrate level, the module level, ..., the final product
      level?

Thanks for any feedback! jw

PLEASE NOTE NEW E-MAIL ID AND USE FOR ALL FUTURE CORRESPONDENCE!

Jerry Wagner  Dept MJ3E  Environmental Engineering  B004-4   Off E006
x56275  pg 58888-0658   (607)755-6275   fax: (607)755-6282
Huron Real Estate Associates, LLC  and  Endicott Interconnect Technologies,
Inc.
Via the Internet: [log in to unmask]  [NOTES: Jerome Wagner/Huron/EIT]

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