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March 2003

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Subject:
Re: Test coupon for Impedance Control Board.
From:
Karl Sauter <[log in to unmask]>
Reply To:
Karl Sauter <[log in to unmask]>
Date:
Wed, 19 Mar 2003 09:11:00 -0800
Content-Type:
TEXT/plain
Parts/Attachments:
TEXT/plain (169 lines) 
Re: IPC-2141

To add to the points that Hans makes:
1) Internal layer theiving in the impedance coupon area can be used to mitigate
low pressure concerns and external layer theiving in the same area can be used
to help ensure more representative external layer impedance test traces (plated
at same local current density).
2) It is a good practice for PWB manufacturers to run towards the high side of
the customer impedance requirement when using standard impedance coupons in the
border area.  Why?  Because the actual on-board traces typically run closer to
PTH's and can be subject to crosstalk during board operations, both of which
usually drive down the functional impedance.

  Karl Sauter, Staff Engineer
  VLSI/Advanced Component Engineering
  Sun Microsystems Inc.
  (650) 786-7663


> Date: Wed, 19 Mar 2003 14:45:41 -0000
> From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
> Subject: Re: [TN] Test coupon for Impedance Control Board.
> X-To: "TechNet E-Mail Forum." <[log in to unmask]>
> To: [log in to unmask]
>
> Hi Raghavendra or should I call you Rao,
>
> A plea from a former lamination guy.
>
> Please keep the realities of the manufacturing process in mind.  The
> impedance coupons I remember didn't have alot of copper - hence an area of
> reduced pressure. To make matters worse the artwork department would place
> the coupon in the panel border area.  This are might not be representative
> of the board area.  The result, a coupon that might pass impedance testing
> when the boards wouldn't or a coupon that would fail when the boards were
> fine.  If the lamination cycle was borderline for the design we'd get resin
> voids in the coupons.
>
> It's been a while since I got my hands dirty (in pcb fab at least) so if
> I've got something wrong speak up.
>
> Hans
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> AC-130 Systems Engineer (Hardware)
> Warner Robins Air Logistics Center (WR-ALC)
> 226 Cochran Street
> Robins AFB, GA 31098-1622
> Tele: (478) 926 - 5847 [DSN Prefix: 468]
> Fax: (478) 926 - 4911
> mailto:[log in to unmask]
>
>
> -----Original Message-----
> From: Brian Butler [mailto:[log in to unmask]]
> Sent: Tuesday, March 18, 2003 9:40 PM
> To: [log in to unmask]
> Subject: Re: [TN] Test coupon for Impedance Control Board.
>
>
> Raghavendra,
>
> The IPC publishes a standard IPC 2141 document which discusses HIgh
> Frequency design issues including controlled impedance coupon design. The
> document is available from IPC at www.ipc.org. (This document is currently
> under revision).
>
> Sincerely,
> Brian Butler
> Introbotics Corporation
>
>
> At 05:43 PM 3/18/03 +0530, you wrote:
> >Hello everybody,
> >
> >I am in the process of design of Test Coupon for the fabrication of
> >Impedance Control Board.  Kindly help me by sending inputs regarding the
> >points to be considered for design of test coupon for Impedance Control
> >Board.
> >
> >Is any one is having detailed drawing or Gerber of test coupon?
> >
> >Raghavendra Rao
> >[log in to unmask]
> >
> >
> >
> >
> >
> >
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