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Subject:	IPC-9701 Daisy chaining LCC's
From:	Steve Constantine <[log in to unmask]>
Reply To:	TechNet E-Mail Forum.
Date:	Thu, 23 Jan 2003 07:53:16 -0600
Content-Type:	text/plain
Parts/Attachments:	text/plain (44 lines)

We are in the process of qualifing a 36 pin SMT LCC package for
solderability. The questions are:

1.If we design a test board with 10 LCC units on it, do we daisy chain each
unit individually and tie all 10 units to a common point? or do we daisy
chain all 10 units consecutively?

2. Do we add jumpers or testpoints in various locations around each
individual LCC to help determine where failures may be?

3. If we do tie all 10 units consecutively, do we add jumpers or testpoints
between each set of daisy chained LCC to help determine which unit has
failed?

4. The IPC-9701 spec calls out that a minimum of 50% of the land pad sites
are to require vias, does this mean that out of the 36 pads being used, at
least 18 have to have a via going through them....and does this mean
directly on the pad itself or coming off the pad like what would most likey
be done during standard PWB layouts?

5. The spec also calls out a nominal of 40% copper coverage on odd number
layers, I'm assuming this means even if that layer is not being used...and
the same would go for the even number of layers which is to recieve 70%
nominal.... am I right in assuming this?

The answers mat be straight foward but as a first time designer using this
spec it has me questioning a lot of the requirements. I appreciate your
help in any way.

Best Regards,
Steve Comstantine
[log in to unmask]

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