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January 2003

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Subject:
From:
Bev Christian <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 16 Jan 2003 16:05:42 -0500
Content-Type:
text/plain
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text/plain (60 lines)
Mel,
Ormet!  Yes, that's the one I meant when I answered Steve.  Nortel had that stuff jump through every conceivable test imaginable.  Its a wonder the Ormet people didn't shot us, it took years to do all the tests.
Bev

-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: January 16, 2003 3:15 PM
To: 'TechNet E-Mail Forum.'; Bev Christian
Subject: RE: [TN] Purposefully shorting two adjacent SOIC leads.


Hi Bev,
As an option, you might look at  http://www.ormetcircuits.com/ . In fact, maybe you are familiar with the process since they reference Nortel qualification. 

Mel Parrish
Director, Training Materials Resources
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
www.solderingtech.com

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Thursday, January 16, 2003 1:01 PM
To: [log in to unmask]
Subject: [TN] Purposefully shorting two adjacent SOIC leads.


Technetters,
How do I do what is proposed in my title?  The options are using excess solder or using a mod wire.  Are there other options for doing this mod?  What do people do?  What is allowed and not allowed by IPC standards (I couldn't find anything, but then I may not be looking in the right place.)  I would expect option one would be a whole heck of a lot easier than option 2.  As long as option 1 doesn't produce bulbous joints with the solder all the way up to the component body is there any real reason why I can't do this?

regards,
Bev Christian
Research in Motion

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