You're right about the extra design effort improving reliability, so I'll
have to reconsider my long-held position. Thanks for pointing this out.
The potential decreased reliability of holes with aspect ratio greater than
4 is downright scary, as I routinely use 10 mil vias in 0.062" boards. I
can see where this could be the case for environments with wide and rapid
temperature swings, but do you think it could be a problem in benign
commercial environments as well? The large number of boards out there with
6:1 aspect ratios suggests otherwise, but we often don't recognize a problem
until someone, well, shows it's a problem. Please, don't tell me what I
don't want to hear, which is that all my boards out there may be time bombs.
Maybe I should switch professions before the fuses run out?
I'll try to post this to TechNet, though some of my messages have been
rejected as well. Must be some server quirk.
Regards,
Seth Goodman
Goodman Associates, LLC
Verona, WI
USA
tel +1 608.833.9933
fax +1 608.833.9966
> -----Original Message-----
> From: Guy Ramsey [mailto:[log in to unmask]]
> Sent: Thursday, October 03, 2002 1:52 PM
> To: [log in to unmask]
> Subject: RE: [TN] PCB design with mask over vias.
>
>
> Great discussion for the technet, for some reason my messages are being
> rejected right now. But person to person, I disagree in as much the
> effort to improve the design will improve reliability. I have seen data
> from three different sources that suggests aspect ratios of greater than
> 4 are less reliable than class three solder fillets on 1206 capacitors.
> I wish the test results could be made public but they simply won't do
> it. It reflects badly on the very people that gathered the data.
>
> Imagine a board house publishing stuff like that. Right off the bat
> their competition would attempt to prove that they can do it and make
> them look like fools. Trust me the guys with the data were not fools.
> Check out IPC-D-279 there are hints in there.
>
> > -----Original Message-----
> > From: Seth Goodman [mailto:[log in to unmask]]
> > Sent: Thursday, October 03, 2002 2:35 PM
> > To: Guy Ramsey
> > Subject: RE: [TN] PCB design with mask over vias.
> >
> >
> > Guy,
> >
> > You are quite right that too many designers use the tightest
> > feature on a board as their default design rule. Every brand
> > of PCB layout software I've ever used lets you use different
> > via types and trace width/spacing at your discretion. My
> > present software, PADS PowerPCB, allows conditional design
> > rules to be specified at the net, net class, component or
> > component pin level AND in addition by layer. There is
> > really no excuse for designers not loosening up the design
> > rules where density is not needed to improve overall yields.
> >
> > However, I do feel the fabricators are largely to blame for
> > the designers' present attitude. IMHO, it is due to their
> > practice of quoting a board based on the tightest design rule
> > used, even if it is only between one trace and one pad. In
> > asking them about this, they have staunchly replied that the
> > price is the same regardless of whether the tight spacing is
> > present in only one spot or on the whole board. They admit
> > their yields will be better if less of the board uses the
> > tighter spacing, but their pricing does not take this into
> > account. Without any cost savings on the board, the designer
> > would be wasting his employers' money if he put in the extra
> > effort to improve the fabricators' yield. After all, it is
> > easier to design any board with finer lines/spaces and
> > smaller vias. In the fabricators' defense, this practice
> > makes quoting much simpler, but they are insuring that
> > designers do the wrong thing. People DO extra work when it
> > is to their economic advantage and tend not to when there is
> > no return. The answer, IMHO, is for fabricators to learn how
> > to estimate yield more quickly from design files and quote
> > accordingly to make it worthwhile for the designer to do the
> > right thing.
> >
> > Regards,
> >
> > Seth Goodman
> >
> > Goodman Associates, LLC
> > tel 608.833.9933
> > fax 608.833.9966
> >
> >
> > > -----Original Message-----
> > > From: Guy Ramsey [mailto:[log in to unmask]]
> > > Sent: Thursday, October 03, 2002 7:14 AM
> > > To: [log in to unmask]
> > > Subject: RE: [TN] PCB design with mask over vias.
> > >
> > >
> > > Your point is well taken. We both know, too well, that
> > design always
> > > involves compromise. The problem, the one that started this thread,
> > > appeared to be a design that failed to recognize high aspect ratio
> > > holes as a compromise. It think the solution is stated, but often
> > > ignored, in IPC-2221. 1.6.3 Complexity Level . . . The complexity
> > > levels (A, B, C) are not to be interpreted as a design requirement,
> > > but a method of communicating the degree of difficulty of
> > a feature
> > > between design and fabrication facilities. The use of one
> > level for a
> > > specific feature does not mean that other features must be
> > of the same
> > > level. Selection should always be based on the minimum need . . .
> > >
> > > As I recall, the situation this was a through hole board with low
> > > component density. Software standard vias should be as large as
> > > possible. If you need to compromise in specific areas of
> > the design,
> > > okay. But changing ones standard via to one suitable for
> > use under .5
> > > or .8 mm pitch BGA is not appropriate. The rub is that many of the
> > > vias will likely be associated with the difficult
> > component, perhaps
> > > more than half of them. It is tempting to just adopt the more
> > > difficult feature requirement as standard (a bad idea IMHO).
> > >
> > > What to do with a .8 mm BGA. In a low risk application with benign
> > > environment you can probably reduce the via size and have good
> > > success. Success will be supplier dependent. High rel harsh
> > > environment? I think the jury is still out. Pad in via filled and
> > > plated might be an answer. We have some testing to do don't
> > we. These
> > > are high density designs IPC/JPCA-2315 has some useful design
> > > guidelines but they are expensive.
> > >
> > > > -----Original Message-----
> > > > From: TechNet [mailto:[log in to unmask]] On Behalf Of Seth Goodman
> > > > Sent: Thursday, October 03, 2002 12:46 AM
> > > > To: [log in to unmask]
> > > > Subject: Re: [TN] PCB design with mask over vias.
> > > >
> > > >
> > > > Guy,
> > > >
> > > > I can't disagree that a 3.5 aspect ratio hole is easy to drill,
> > > > plate, clean and it is reliable. However, for an 0.062"
> > board, this
> > > > means an 18 mil finished hole size via, which then
> > requires a 33 to
> > > > 38 mil pad. It also requires a 48 mil anti-pad on the
> > inner layers.
> > > > We are talking some serious real estate here.
> > > >
> > > > This becomes a big problem when we use 6 mil line and
> > space rules to
> > > > route between 0.8mm pitch BGA's. With via pads and
> > anti-pads this
> > > > big, increasing the layer count won't always make a
> > design routable.
> > > > We can make the board thinner to allow smaller vias, but
> > only when
> > > > the board itself is physically small. What's your
> > opinion (besides
> > > > use
> > > > microvias) when we need high routing density on an 0.062" thick
> > > > board?
> > > >
> > > > Regards,
> > > >
> > > > Seth Goodman
> > > >
> > > > Goodman Associates, LLC
> > > > Verona, WI
> > > > USA
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Guy Ramsey
> > > > > Sent: Friday, September 27, 2002 4:54 PM
> > > > > To: [log in to unmask]
> > > > > Subject: Re: [TN] PCB design with mask over vias.
> > > > >
> > > >
> > > > ----------- snip -------------
> > > >
> > > > > Can they increase the via size? I am a firm believer in
> > > > aspect ratios
> > > > > less than 3.5.
> > > > >
> > > > >
> > > > >
> > > > > Guy Ramsey
> > > > > Senior Lab Technician/Instructor
> > > > > American Competitiveness Institute
> > > > > E-Mail: [log in to unmask]
> > > > > Ph: (610) 362-1200 x107
> > > > > Fax: (610) 362-1290
> > > >
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> >
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>
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