I've wondered about this for some time, as well:  to mask or not to mask,
that is the question.  Here are a few scenarios with some plus and minus
info, but I still can't answer the question.

1) Mask vias both sides, no filling:  risk of flux entrapment due to
imperfect LPI mask coverage; long-term failure risk due to corrosion,
strongly dependent on service environment.

2) Vias open both sides:  increased opportunity for shorts due to imperfect
masking of adjacent traces (this is a PCB defect) and due to bridging if the
board is wave soldered (this is a process defect); in other words, this can
make the design less robust.

3) Fill vias, then mask both sides:  some risk if fill is not totally cured;
otherwise only problem (for designers and CM's) is increased PCB cost.

4) Mask vias top side only:  I've done this at the request of CM's who want
bottom side test access and a vacuum seal; I worry about how well we can
clean a 6:1 aspect ratio blind hole; I have never liked this option.

It seems like the above failures fall into two categories:  immediate and
long-term.  The immediate failures reduce yield but can be picked up at
final test (groan).  This is not free, but at least you don't ship bad
product.  The long-term failures are highly dependent on the environment
that the product lives in.

The obvious answer for the long-term failures is to use accelerated aging
tests and qualify the entire process for the product environment.  This may
be the only way to go for hi-rel, large-budget projects.  However, it is not
very practical for lower-volume commercial work.  This is where some
sensible guidelines are needed.  For benign commercial product environments
(indoor, human occupied spaces without severe temperature or humidity
swings, no severe chemical atmosphere, etc.), class one or class two
acceptance criteria, ten-year product life expectancy, what is a reasonable
approach?  Every PCB fabricator and CM I speak to has a different opinion.
Can we as an industry reach some consensus on this?

Regards,

Seth Goodman

Goodman Associates, LLC
Verona, WI
USA

---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------