The J-STD-001 does address your situation, depending on the class of the
product. For Class 3 OA fluxes with L1 activity levels must be cleaned.
It is possible that the paste you are using is more active than L,
perhaps M or even H. In this case, you are in dangerous territory. The
standard states that M and H fluxes are suitable only for tinning lead
and solid wire. We have seen M and H fluxes used in manufacturing lines.
I consider this a process defect. Others will disagree, because the
HDBK-001 says that Type M flux was added as an option for Class 3
products. I don't see it in the standard. If you choose that path there
are some rather strict cleaning qualification requirements.

Even so, we have seen many instances where manufacturers using M0 and M1
flux pastes thought they were cleaning adequately only to find out that
they were not.

Now lets point the standards at your customer. The J-STD-001 states that
the User is responsible to identify defect criteria that are unique to
the product. Coating is a process that might impose special acceptance
criteria on a Manufacturer (both board supplier and CM).

Perhaps, IPC-SM-840 also points back to your customer, though it might
come as a surprise to them. 3.6.1.1 Resistance to Solvent and Cleaning
Agents; requires the mask to survive only a few minutes exposure to low
temperatures of DI water and the types of solvents you are likely to be
using. Specifically, section 6.2 of the standard states, "For this
reason, the user is urged to utilize this specification as a basis to
construct a customized procurement document in conjunction with his
supplier to consider the inclusion of special requirements in the
procurement documents, especially in the following areas
(a) coating thickness
(d) solvents and fluxes
(e) printed board assembly and operational requirements
(f) conformal coating

All that said, did your customer know you were using a very aggressive
flux, and (attempting) water cleaning? It all leads back to J-STD-001.
If you are using non standard processes you are required to develop
acceptance criteria. If the user has non-standard requirements, they
need to develop acceptance criteria.

What to do. Perhaps merely opening vias would provide enough cleaning.
Perhaps opening the vias and printing paste so as to fill the hole would
work. Can they increase the via size? I am a firm believer in aspect
ratios less than 3.5.



Guy Ramsey
Senior Lab Technician/Instructor
American Competitiveness Institute
E-Mail: [log in to unmask]
Ph: (610) 362-1200 x107
Fax: (610) 362-1290





> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Willie Duersch
> Sent: Friday, September 27, 2002 3:01 PM
> To: [log in to unmask]
> Subject: [TN] PCB design with mask over vias.
>
>
> Hello Peers:
> We are a CM who recently fabricated a PCBA which had the vias
> covered by solder mask film design on the PCB. This is not
> the first time we have seen this done in PCBA. However, in
> this example, the PCBA ended up inside a refrigerator. This
> customer adds few notes with the PCB and nothing was
> specified associated with the fab on plugging or capping of
> the vias. The PCBA did not require wave solder. Aqueous clean
> paste was used and PCBA washed after SMT.
>
> The PCBA was supplied to the customer who then selectively
> applied Conformal coating over the top side components on the
> board with a brush, but did not coat other through holes or
> vias on the component side or any area of the back side.
>
> Over a period of time, The vias on the back side showed
> evidence of corrosion and subsequent cross section analysis
> showed copper corrosion from the pad part way into the barrel
> even under soldermask. The cross section also showed that the
> LPI solder mask did not plug and did have pin holes in the
> mask with bare copper in the air pockets that occur during
> LPI screen deposition. 1. We feel the customer is responsible
> to specify the PCB and PCBA performance criteria. Comments?
> 2. Is there an IPC document that covers solder mask covered
> vias and guidelines associated with the practice? If not, why
> not? 3. Is it the PCB shop or the CM who should question, and
> if not specified...should either question the practice? 4.
> What are the issues related to designing with solder mask
> film design covered vias? In this case, the vias were
> .010-.014 diameter and space constraints were not an issue.
> There were other holes on the PCB that were larger diameter
> and were left open to coat with solder from the HASL
> operation...and not coated with conformal coat. 5. What would
> you tell a customer to correct the issue?
>
> There are some obvious issues and answers and I have had 12
> years of experience with PCB's. However, I really would like
> to have some comments from my peers. Best regards, Willie

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