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September 2002

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Wed, 4 Sep 2002 07:46:08 +0800
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HI, Mark,

I agree exactly with Carrie, with the slight addition that their paste may
also be 'old' and the volatiles that provide the wetting action have
disappeared. Or the paste could just contain a flux that isn't sufficiently
active (this should not be very likely, though.

Peter



"Morse, Carrie" <[log in to unmask]>   03/09/2002 08:17 PM
Sent by: TechNet <[log in to unmask]>

Please respond to "TechNet E-Mail Forum."; Please respond to "Morse,
Carrie"

              To:  [log in to unmask]
              cc:  (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
              Subject: Re: [TN] poor wetting- pcb or assy problem?








My first guess would have been high tin content on the HASL, but, if the
HASL's OK, then my next best guess is the reflow profile.  Has the CM run a
board through the oven with a Mole to measure the actual board temps at the
sites not reflowing?  If it's not the profile, my next guess is  the paste
... maybe it's lead free and has a higher melting point than they expect.



-----Original Message-----
From: Mark Hargreaves [mailto:[log in to unmask]]
Sent: Friday, August 30, 2002 2:59 PM
To: [log in to unmask]
Subject: [TN] poor wetting- pcb or assy problem?


Hi All,
We shipped 52 bare boards to our customer, who hand assembled 2, and then
sent 50 to a contract manufacturer for assembly.  The assembly house
soldered the surface mount caps (paste & oven) and stopped because the
solder was not "wetting".  (there were apparently no problems with the hand
assembled boards).  I saw 4 of the partially assembled boards- they look
ugly.  The HASL solder covers the entire pad (no copper showing), but the
paste solder doesn't flow to the pad edges.  It looks like the two solders
don't want to combine.
The bare board HASL finish (vertical HASL) looks typical, the HASL solder
content was analyzed (ok) the previous week, and the solder pot was skimmed
that morning.

So, we sent a spare bare board from the same lot to a test house for J-std
3, test A (dip test), which it passed.

The assembly house says the bare boards are at fault, and that the dip test
is less demanding than the paste/ I/R oven process used on these boards.

Any ideas as to the root cause?

Is there a straight forward way to verify this?

It's been a year since we received our last solderability complaint.  That
ended in inconclusive discussion regarding "intermetallics".  I'm hoping to
resolve this one more logically.


Thanks,
Mark Hargreaves

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