Alcon:
- Regarding plating thickness.  Historically the plating thickness for the
Nickel barrier plating was defined by QQ-N-290 and the thickness for Au
plating was specified by Mil-G-45204. If the Au plating was less than 50
microinches thick it was considered a reliability risk due to porosity
associated with thin coatings.  The acceptable range was 50 to 100
microinches.  A coating thickness between 50 and 100 was considered
solderable after one tinning operation to leach/remove the majority of gold f
rom the surface.  If a surface had more than 100 microinches then it had to
be tinned twice to affect the removal of additional gold.  Those requirements
worked pretty well in keeping the gold below 3% in most solder connections.
Take into account that back then most components were 50-mil or larger and
the pwb termination areas were equally large, so you had a lot of solder
quantity in the finished connection.
- With the reduced component and circuit board geometry's that are in use
today I don't think the older requirements referenced above should be
followed for surface mount component attachment.  I believe that the less
stringent requirements of IPC-J-STD-001 (gold removed from at least 95% of
the surface to be soldered for PTH components if gold thickness exceeds 2.5
um [100 microinch]) are a good guideline (but need to be applied with some
forethought and common sense). The same paragraph says that for SMT gold has
to be removed from 95% of the to be soldered surfaces, regardless of
thickness.
- In today's world a circuit board that is provided with gold plated
solderable surfaces should have relatively thin plating (10 to 15
microinches) and, needless to say you are going to solder directly to the
gold surface without tinning (which would leave you with a mound of solder at
each termination instead of a nice flat area).  The catch 22 seems to be that
with plating that thin you need to pay attention to storage/humidity
conditions before the pwb's are assembled.  JIT works well in that
application, but controlled storage works equally well and has a more
tranquilizing effect on manufacturing engineers and production expediters
- Under ideal conditions you would evaluate and control your process by
overplating (with nickel) the gold plated sample coupon from a panel,
microsection it and measure the thickness of the gold.  Next, run a
production sample and examine the resultant solder connections for percentage
of gold.  When you receive a different lot of pwb's, do the same thing again.
 After two or three exercises like that you should have enough data to relate
the percentage of gold in the solder connections to the gold thickness on the
pwb's (presuming your process is in control and solder paste deposition and
all other elements remain unchanged).
- The gold removal requirements, like most requirements, are a little
dependent on the design and the materials in use.  Major elements to consider
are the size of the components in their largest dimension, the compliance of
the lead (if any) design & material and the Tce/Cte differential between the
component and the pwb. Generally speaking 3% is the maximum allowable for
most applications.
- Just some thoughts from an old codger, hope it helps a little.
Regards, Jim Moffitt, Moffitt Consulting Services