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Reply To: | TechNet E-Mail Forum. |
Date: | Mon, 19 Aug 2002 09:45:46 -0600 |
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What JEDEC, IPC or other specifications or guidelines address voiding in
underfill between components (molded packages, flip chips, etc) and PC
boards/substrates, or if there already exists such a list somewhere? Thanks.
Syed.
Syed Sajid Ahmad
Advanced Packaging Technology/Fab 4 Mail Stop 718
Micron Technology, 8000 S. Federal Way, Boise ID 83716-9632
(208)368-3359 Fax (208)363-2994
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