I was going to answer in much the same way when this thing first posted but
CAF emerged. Seen way too many chip device destructions during touch up. You
got to get the solder joints right the first time after good DFM/CE
practices using proper design rules, component selection, and a clear view
what of what you're going to get when you lay down your often silly ass RF
requirements that can't be (made manufacturable because some RF types won't
try it because it don't look right on paper - yet) built half or more of the
time.

Now I'm receiving word from on high we cannot use blind plated over vias,
placed way too clocely together, to support 500 Mhz decoupling caps because
they quit working by I000 Mhz and above as their value goes away. So now,
we're supposed to place Vcc and ground vaias on ten mil hole centers or
less. Jeez, my latest CAF is getting to me. This seems a real step backward.
What about buried capacitance for this stuff.

MoonMan

---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------