Patrick,
You have asked one of the most important questions to date on this forum. I
have asked the other many times. The following is a set of MASTER DRAWING,
not fab drawing, NOTES I have all clients place on their MASTER DRAWING:
POD MASTER DRAWING NOTES
1.0 Laminate, Core, and Prepreg Material
1.1 Laminate, core, and prepreg material shall conform to IPC-4101 requirements.
1.2 Laminate, core, and prepreg shall be FR-4 with a minimum Tg of 170
degrees C.
1.3 Laminate, core, and prepreg shall be U.L. recognized at 94 V0.
1.4 Conductive foil shall be electro-deposited copper unless otherwise
specified.
1.5 External and internal foil shall be .5 oz. copper unless otherwise
specified.
1.6 Overall MLB and individual dielectric thickness shall be + or - 10%.
1.7 Fabricator may adjust overall and individual dielectric thickness to
meet impedance requirements indicated on this drawing.
1.8 Fabricator may use single ply constructions unless otherwise specified.
1.9 There shall be no 7628 glass style prepreg used facing copper. If
required, single or multi-ply 7628 core material may be used. If used as
prepreg, 7628 only may be used between two other more resin rich glass styles.
1.10 Multilayer constructions shall conform to graphic on this drawing.
1.11 There shall be no evidence of SMT pad lifting after thermal stress
testing or during assembly operations.
2.0 Hole Requirements
2.1 Laminate Voids Outside Thermal Zone (IPC-A-600F, 3.1.1&4).
2.2 Hole drilling and preparation requirements shall conform to IPC-A-600F
with positive etch back preferred (3.1.5.1&2).
2.3 Dielectric Material, Clearance, Metal Planes (IPC-A-600F, 3.1.6).
2.4 Lifted Lands (IPC-A-600F, 3.3.2).
2.5 Plating Cracks (IPC-A-600F, 3.3.3-6).
2.6 Plating Nodules (IPC-A-600F, 3.3.7).
2.7 Plating Voids (IPC-A-600F, 3.3.9).
2.8 Wicking (IPC-A-600F, 3.3.11.1).
2.9 Inner Layer Separation (IPC-A-600F, 3.3.12).
2.10 Burrs, Nail Heading (IPC-A-600F, 3.4.1&2).
2.11 All finished plated hole dimensions and tolerances shall conform to
this drawing?s drill chart.
2.12 All plated hole tolerances shall be + or -0.003? unless otherwise
specified.
2.13 Non-plated tooling holes shall be as specified + 0.003? -0.000?.
2.14 Plated hole internal annular ring tangency/breakout allowed except at
pad/trace interface.
2.15 Plated hole external annular ring requirements shall be .001? minimum.
2.16 Fabricator adjustments may be made to meet annular ring requirements,
as teardrop additions, provided no other violations effected.
2.17 Blind vias may be laser ablated and shall meet plated hole requirements
of IPC-A-600F.
3.0 Conductor Width and Spacing
Unless otherwise specified on this drawing, as in the multilayer
construction graphic, the following nominal trace widths and spaces shall be
used:
3,1 Outer layer conductor widths shall be .005?
3.2 Outer layer conductor spacing shall be .005?
3.3 Inner layer conductor widths shall be .005?
3.4 Inner layer conductor spacing shall be .005?
4.0 Hole Plating and Solder Termination Area Coating/Plating
4.1 All electroless copper deposition, and electroplated copper requirements
shall meet IPC-A-600F and IPC-6012 specifications.
4.2 All plated holes shall meet IPC-A-600F, Class 2 requirements with an
average plating thickness of .001? and a minimum of .0008? with minimum
acceptable voiding (IPC-A-600F, 3.3.8&9).
4.3 Solder termination area (surface mount lands and plated through holes)
coating/plating shall be immersion gold (0.000002? ? 0.000010?) over
electroless nickel (0.000110? minimum).
4.4 Fabricator shall supply solder samples, using test coupon ?E? and
x-sections before and after thermal stress using test coupons ?A? and ?B?,
respectively, IPC-A-600F, IPC-6012, and IPC-TM-650 requirements.
Note: Two quality conformance test circuits are supplied with each MLB
design. One shall be used by the supplier for testing per note 4.3 and shall
be returned to POD, after having been made traceable to each board. The
other shall be returned, untested, to POD after having been made traceable
to each board supplied. Quality conformance test circuitry shall be placed
as indicated on this drawing and/or IPC-2221 figure 12-1.
4.5 Maximum non wetting or dewetting shall not exceed 1% overall and 5% on
any solder termination SMT pad or through hole. No evidence of ?black pad?
shall be apparent after solder testing and/or soldering operations.
4.6 Thieving shall be allowed except in R/F circuit areas.
4.7 Maximum non wetting or dewetting shall not exceed 1% overall and 5% on
any solder termination SMT pad or through hole. No evidence of ?black pad?
shall be apparent after solder testing and/or soldering operations.
4.8 Thieving shall be allowed except in R/F circuit areas.
5.0 Solder Mask and Marking
5.1 Solder mask/resist shall be liquid photo imageable (LPI) meeting
IPC-A-600F, 2.9 - Class 2 requirements.
5.2 Solder mask/resist registration shall meet IPC-A-600F, 2.9 - Class 2
requirements for all component mounting or attachment lands/pads, including
BGA, with no resist encroachment on pads except where specified.
5.3 All prototype board top side vias shall be ?tented? with solder mask
(IPC-7095, 5.4.4) until otherwise specified for production boards.
5.4 BGA pads shall not be solder mask defined and no solder mask shall
encroach or otherwise be apparent on pads except ?tented? via holes.
5.5 All bottom side vias shall not be ?tented? with solder mask.
5.6 Marking ink shall be white, non-conductive, epoxy on sides required.
5.7 Marking shall be clear, legible, and permanent meeting IPC-A-600F, 2.8 -
Class 2 requirements.
5.8 As with solder mask, no marking ink shall encroach or be apparent on
solder termination pads or areas.
Note: the above notes concerning tenting apply only to prototype boards or
others as separately specified.
6.0 Fabrication Requirements
6.1 All final fabrication requirements (edge conditions, cut outs, etc)
shall meet IPC-A-600F, Class 2 requirements.
6.2 Unless otherwise specified, bow and twist requirements shall be .75% in
accordance with IPC-A-600F, Class 2 requirements for all BGA and fine pitch
SMT boards. 1.5% is acceptable on other board types unless otherwise specified.
7.0 Test Requirements
7.1 All electrical, including time domain reflectometry, and physical test
requirements shall be met in accordance with IPC-A-600F, IPC-6012, and
IPC-TM-650 test method requirements.
7.2 For all impedance controlled MLB?s, the fabricator shall provide
x-sectional correlation to TDR findings that clearly show and define each
dielectric thickness, glass style, copper foil thickness, plating thickness,
and laminate area and thermal zone evaluations as received and after thermal
stress ? as in 7.1.
7.3 Two photo micrographs shall be provided for each quality conformance
test circuit per lot. One shall show one hole on the ?A? coupon, in an as
received condition, and one shall show one hole on the ?B? coupon, after
thermal stress. This shall be done for each mutually agreed upon lot. Each
photo shall be taken at 40X and shall clearly verify the fabricator?s
microsection report, and shall directly correlate to the report?s findings.
SPECIAL NOTES:
7.4 Impedance in the R/F section of this board shall be 75 ohms. On the DC
section, impedance shall be a function of materials, constructions, and
trace widths.
7.5 Other special notes as required.
I consider it good if I even get solderablility issues resolved. I have
never, no matter how hard I tried, gotten cleanliness issues resolved this way.
I wish us all the best with the cleanliness and solderability issue.
However, I will say that Cisco once almost succeeded on both.
Earl Moon
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