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July 2002

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Subject:
From:
"Ingemar Hernefjord (EMW)" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 2 Jul 2002 08:49:16 +0200
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Hi Earl,
you seem to cover most in those few lines
I would add this first thing I did: use only highly skilled operators (unless you see 'capabilities' below as human resources). Best guarantee, better than good engineers....gosh...I'll be in bad situation now...
Best regards
Ingemar Hernefjord
PS. unwritten rule here : never let in an engineer in the production! Bit of black humour, but with great deal of truth.

-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: den 1 juli 2002 19:14
To: [log in to unmask]
Subject: [TN] FAULT/DEFECT TEST STRATEGY


Folks,

I am not a test engineer but having to do catch up quickly to develop a
sensible test strategy to find faults and/or defects usin a combination of
test disciplines and elements. Watched my board designer spend a very long
time placing 1800 test points, some not on grid, as something of an
experiment on a non-HDI, but approaching it, and didn't like the results.

I'm hoping some of you can offer positive, or negative, criticism concerning
the following summary I've come up with though probably not new to you all:

SUMMARY
When considering a new, fairly complex, high density PCB design (defined
often on the basis of how many and what pitch area array devices are
required) with limited test probe access for ICT, the following
considerations should be met:
1) Ensure only highly qualified board fabrication capabilities are used.
This must be done to provide printed circuitry that has the highest laminate
integrity, hole quality and reliability, plated or coated surfaces that
solder wet, and the ability to do adequate bare board testing in conjunction
with effective X-Sectional analysis. This will prevent many other defects
during the assembly operation as poor quality solder joints, and shorts or
opens when hole walls fail.
2) Ensure only highly qualified assembly capabilities are used. This must be
done to provide defect free assemblies with high quality and reliability
solder joints, specified component placement and orientation, and the
ability to prove all this with a well thought out test strategy.
3) Ensure a well thought out test strategy is in place consisting of some or
all the following:
?
X-Ray used on all area array devices to ensure high quality solder joints
and the ability to reduce the number of test probe pins and test points
relating to these device types.
?
AOI capabilities to determine solder joint quality for leaded and discrete
SMD?s as well as specified component types with proper orientations,
polarity, and values. This too will minimize the number of test points
required along with attendant bed of nails in those areas shown to meet
specified requirements.
?
The use of boundary scan in those circuit areas deemed viable for such testing.
With all the above, it is possible to create and implement a test strategy
capable of providing for all test requirements for our board types but RF. I
am studying a R/F test plan.


Earl Moon

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