Hi, Earl,
I'm no test engineer either, so cannot comment in any real depth on your
summary, but offer what I can.
1. Considerations for design and layout of high-density, complex boards
starts with the type of board you're dealing with in terms of
(a) how is it to be cooled ?
(b) how much does it need to be cooled ?
(c) which are likely to be the hottest-running components (to be placed in
the most advantgeous positions on the thermal path) ?
(c) which components must be kept close together for functionallity ?
(d) what test method is to be used (ICT, simulation, etc) to determine
method of test access (test point on each net or test access connectors)?
(e) test pad size requirements, based on probe
costs/affordability/sizes/tolerences.
(f) locations and sizes of keep-out areas for attachments of mechanical
parts.
(g) assembly processes to be used (esp. soldering)
(h) determination of pad:hole diameter ratios (partly determined by fab
house capability and board material, and partly by board material,
soldering process to be used and particular component idiosynchracies).
(i) trace width/spacing
(j) critical traces (max lengths from specific points)
All the above have to be assessed by various different disciplines and then
juggled together to get a layout that stands a chance of working. ICT test
points take up a lot of real estate, particularly for high-density boards
with possibly thousands of nets. Each net needs at least one test point,
but a skilled test engineer should be able to determine component clusters
that can be tested using boundary scanning and advise the board router
accordingly. This can greatly reduce the number of test points needed,
freeing up real estate and giving the poor router more breathing space to
achieve a layout within the prescribed design rules. It's a
multi-dimensional jigsaw puzzle that is as much art as science.
I would be worried about ICT test points not being kept on a grid, as this
will increase jig costs.
2. I would suggest that board design/layout and a test strategy have little
or nothing to do with the quality of PCB fabrication or its assembly -
though PCB quality, and the assembly processes used, could well affect the
test results you obtain using the strategy. Very high quality boards at all
levels of manufacture make passing tests easier and can reduce diagnosis
time, but I would say a test strategy is (or ought to be) still independant
of manufacturing quality.
3. A test strategy should address:
(i) test method to be adopted (ICT, simulation, etc)
(ii) fixed jigs or flying probes (cost and through-put time dependant)
(iii) what is to be tested, when and how (some areas may require manual
testing if ICT, or whatever, cannot be accommodated).
(iv) what about levels of test - not just for boards but other
mechanical/electromechanical/electro-optical/opto-mechanical assemblies?
(v) what about ESS, EQT, HASS, HALT, burn-in, etc - these too must be
included as required in a test strategy.
It should avoid overlapping into other areas such as Inspection (viz AOI,
AXI and so on).
4. Point of information: X-Ray Inspection, even if you have access to some
very good 3-D machinery with computer filtering and enhancement, will not
guarantee you proof of first class solder joints. Interpretation of X-Ray
images, even the clearest possible needs an expert, and that becomes a
variable with wide tolerence margins. Surface texture of area array solder
joints and their attachment to pads is still difficult to judge from X-ray,
unless it's quite gross.
Each AAD ball will be one point on a net, together with contacts from
numerous other components. To adequately test a net, you still need one
test point at least. Again, quallity of manufacture should be independent
of test strategy, though it can make fault diagnosis easier. Board Design
and Test Strategy should be planning for success or you'll use up too much
real estate trying to cover every contingeny with unnecessary test points.
Leave manufacturing quality for the manufacturing engineers to worry about
adn assume they're doing their job, unless you know otherwise.
Enough rambling, but hope I've made some sense.
Peter
Earl Moon <[log in to unmask]> 02/07/2002 01:13 AM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to Earl Moon
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: [TN] FAULT/DEFECT TEST STRATEGY
Folks,
I am not a test engineer but having to do catch up quickly to develop a
sensible test strategy to find faults and/or defects usin a combination of
test disciplines and elements. Watched my board designer spend a very long
time placing 1800 test points, some not on grid, as something of an
experiment on a non-HDI, but approaching it, and didn't like the results.
I'm hoping some of you can offer positive, or negative, criticism
concerning
the following summary I've come up with though probably not new to you all:
SUMMARY
When considering a new, fairly complex, high density PCB design (defined
often on the basis of how many and what pitch area array devices are
required) with limited test probe access for ICT, the following
considerations should be met:
1) Ensure only highly qualified board fabrication capabilities are used.
This must be done to provide printed circuitry that has the highest
laminate
integrity, hole quality and reliability, plated or coated surfaces that
solder wet, and the ability to do adequate bare board testing in
conjunction
with effective X-Sectional analysis. This will prevent many other defects
during the assembly operation as poor quality solder joints, and shorts or
opens when hole walls fail.
2) Ensure only highly qualified assembly capabilities are used. This must
be
done to provide defect free assemblies with high quality and reliability
solder joints, specified component placement and orientation, and the
ability to prove all this with a well thought out test strategy.
3) Ensure a well thought out test strategy is in place consisting of some
or
all the following:
?
X-Ray used on all area array devices to ensure high quality solder joints
and the ability to reduce the number of test probe pins and test points
relating to these device types.
?
AOI capabilities to determine solder joint quality for leaded and discrete
SMD?s as well as specified component types with proper orientations,
polarity, and values. This too will minimize the number of test points
required along with attendant bed of nails in those areas shown to meet
specified requirements.
?
The use of boundary scan in those circuit areas deemed viable for such
testing.
With all the above, it is possible to create and implement a test strategy
capable of providing for all test requirements for our board types but RF.
I
am studying a R/F test plan.
Earl Moon
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