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Reply To: | TechNet E-Mail Forum. |
Date: | Mon, 1 Jul 2002 12:20:05 -0500 |
Content-Type: | text/plain |
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Folks,
I am finishing my third iteration of my DFM/CE check lists. It will be done
about this time next week. I am doing this concurrently while working nearly
in real-time with my designer, management, board house, and assembly
capability plus whatever test capabilities are available.
The boards on which I am working on are semi-high density with some
interesting twists and turns. Of course, other boards from the past are
pushing my progress.
I will ask Daan to post it on his site if willing. It contains specific
parameters, dimensions, tolerances, and references to IPC and other sage
documentation.
Earl Moon
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