Ken
As a standard operating practice when fabricating a part we take the solder
mask layer and use it to clip the silkscreen back from and solderable area.
*GOD BLESS AMERICA*
William W. DeCray III
Waytec Electronics Corp
CAD/CAM & Engineering Services Manager
PHONE:(434) 237-6391 ext 115
CELL: (804) 851-6115
FAX: (434) 237-1324
E-mail:<[log in to unmask]>
Web http://www.waytec.com
FTP ftp://ftp.waytec.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Croslin, Robert
Sent: Tuesday, July 30, 2002 10:46 AM
To: [log in to unmask]
Subject: Re: [TN] Silscreen on SMT pads
Ken, we don't view this as a fabrication problem, but as a design one. We
use p-cad which is a lower end PCB design tool as opposed to Mentor,
Cadence, etc. One of the things it does for us as part of the DRC is to
tell us if we've placed any legend on or near a pad, depending on how we've
defined our keep out areas. The other thing we do is work with our fab
house very closely during the prototype stage to help us look for those kind
of things. Anyway, you may want to talk with your PCB designer to see what
the tool they're using can provide in checking for legend clearance.
Bob
Robert A. Croslin
Manager, Engineering Services
Nielsen Media Research
375 Patricia Ave
Dunedin, FL 34698
727-738-7033
[log in to unmask]
-----Original Message-----
From: Ken Carlile [mailto:[log in to unmask]]
Sent: Monday, July 29, 2002 3:35 PM
To: [log in to unmask]
Subject: [TN] Silscreen on SMT pads
Can anyone kindly tell me if IPC has a guideline for silkscreen on SMT pads?
Our master drawing notes
read: "As with solder mask, no marking ink shall encroach or be apparent on
solder termination pads or
areas". Therefore we have internal reason to reject these, however I was
hoping there was an industry standard.
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