Dear Poh,
I heartily agree with your observation. You can only DFM if you have a M_r
to DF and with. If your CEM isn't appointed by the time design starts, you
can't design around a known manufacturing capability. In which case, what
DO you design, and how? This was the main reason why I continued to
advocate retaining in-house manufacture rather than out-sourcing, after
out-sourcing became all the rage.
Outsourcing does have advantages, though - CEM's are exposed to a far
greater variety of technical innovation than any in-house facility, and the
technical knowledge thus won is useful beyond measure. More has been
contributed to understanding processes and improving general standards
through out-sourcing than was ever the case when in-house facilities kept
their secrets to themselves. There is still no overall standard capability,
though, whereby designers can just design and plug the output into a CEM
for automatic, faultless translation into finished product. Nor will there
ever be if development is not to stagnate. There should be an IPC standard
for how, when and about what individuals in product teams should
communicate with each other. Any takers?
Peter
Poh Kong Hui <[log in to unmask]> 03/07/2002 06:04 AM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to Poh Kong Hui
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
Hi All,
There are many design companies or companies that outsource
the manufacturing & they only focus on design, marketing,
purchasing; once the design is done, they throw all the
design issue to manufacturing companies (the subcon).
In the end, the subcon can complain & complain the design is
not being "DFM", and the customer can tell the subcon
"You are the expert to assemble", and they don't learn.
I have seen many companies who do designwithout manufacturing
do not how to design their product.
They simply dreamt their product the way they want.
Many time we end up handcraft the boards.
Sound crazy !
Poh
At 11:15 AM 7/2/02 -0400, joyce wrote:
>Ken
>the long term payoff is much bigger for someone get their hands dirty. If
>the company can not recognize this, the lost of profit and brand name will
>be in the future (unless, you are the only "game" in town). The delay
>consequence normally get those fast track guy off their responsibility
easy.
>If you get someone design it and support it for the duration of the life
>cycle, guess what, the good/bad designer whould devide very well into 2
>groups.
>
>jk
>
>>-----Original Message-----
>>From: TechNet [mailto:[log in to unmask]]On Behalf Of Ken Carlile
>>Sent: Tuesday, July 02, 2002 10:59 AM
>>To: [log in to unmask]
>>Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>>
>>
>>Joyce:
>>
>>I started in contract manufacturing and have moved into the design
>>realm. I
>>agree that alot of designers need to see a production facility to
>>straighten
>>their heads but the unfortunate situation is it is not feesable. A
company
>>will not pay design engineering money to work in assembly, and
>>unlike myself
>>who used it to work thru college, contract manufacturing does not
>>pay enough
>>to sustain this engineering type. DFM is needed but always the
>>afterthought. My hands are dirty but I am also paying dearly for
>>not taking
>>the fast track to Engineering. Welcome to the 21st century!!!
>>
>>Ken
>>
>>-----Original Message-----
>>From: TechNet [mailto:[log in to unmask]]On Behalf Of joyce
>>Sent: Tuesday, July 02, 2002 8:18 AM
>>To: [log in to unmask]
>>Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>>
>>
>>"some young Design
>>>Engineers don't take DFM seriously".
>>if someone don't know "manufacturing", never set a foot into the
>>manufacture
>>floor, asking DFM is very un-reasonable. Send them to the floor for 6
>>month, you will see the difference. Send them to repair shop for another
6
>>month, you will get your DFR (design for reliability). In the process,
you
>>will get rid of the one who do not want to get their hands dirty too.
>>
>>jk ;-0
>>
>>>-----Original Message-----
>>>From: TechNet [mailto:[log in to unmask]]On Behalf Of Ingemar Hernefjord
>>>(EMW)
>>>Sent: Tuesday, July 02, 2002 5:13 AM
>>>To: [log in to unmask]
>>>Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>>>
>>>
>>>So, so, don't weep dear Peter,
>>>next line may comfort you a little
>>>Production engineers are not included, what we mean are Design
>>>Engineers...woe, woe...now I'll get that beeswarm on myself instead...
>>>Like your humoristic spirit, Peter...
>>>
>>>Severily: DFM is like star of Betlehem, we too try to walk
>>>steadily in that direction.Unfortunately, some young Design
>>>Engineers don't take DFM seriously.
>>>
>>>Ingemar
>>>
>>>
>>>
>>>
>>>-----Original Message-----
>>>From: [log in to unmask] [mailto:[log in to unmask]]
>>>Sent: den 2 juli 2002 10:11
>>>To: TechNet E-Mail Forum.; Ingemar Hernefjord (EMW)
>>>Cc: [log in to unmask]
>>>Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>>>
>>>
>>>
>>>Dear Ingemar,
>>>
>>>I am deeply hurt! (sulk!) What's wrong with us Production
>>Engineers, eh? We
>>>have to make all this hardware so that it works, and it's
>>important that we
>>>have an input to board design. Maybe you're actually a wee Viking devil,
>>>sitting on Earl's left shoulder, tempting him away from the true path of
>>>DFM!?
>>>
>>>Peter
>>>
>>>
>>>
>>>"Ingemar Hernefjord (EMW)" <[log in to unmask]>
>>>02/07/2002 02:49 PM
>>>Sent by: TechNet <[log in to unmask]>
>>>
>>>Please respond to "TechNet E-Mail Forum."; Please respond to "Ingemar
>>>Hernefjord (EMW)"
>>>
>>> To: [log in to unmask]
>>> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
>>> Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>Hi Earl,
>>>you seem to cover most in those few lines
>>>I would add this first thing I did: use only highly skilled operators
>>>(unless you see 'capabilities' below as human resources). Best
guarantee,
>>>better than good engineers....gosh...I'll be in bad situation now...
>>>Best regards
>>>Ingemar Hernefjord
>>>PS. unwritten rule here : never let in an engineer in the production!
Bit
>>>of black humour, but with great deal of truth.
>>>
>>>-----Original Message-----
>>>From: Earl Moon [mailto:[log in to unmask]]
>>>Sent: den 1 juli 2002 19:14
>>>To: [log in to unmask]
>>>Subject: [TN] FAULT/DEFECT TEST STRATEGY
>>>
>>>
>>>Folks,
>>>
>>>I am not a test engineer but having to do catch up quickly to develop a
>>>sensible test strategy to find faults and/or defects usin a combination
of
>>>test disciplines and elements. Watched my board designer spend a very
long
>>>time placing 1800 test points, some not on grid, as something of an
>>>experiment on a non-HDI, but approaching it, and didn't like the
results.
>>>
>>>I'm hoping some of you can offer positive, or negative, criticism
>>>concerning
>>>the following summary I've come up with though probably not new
>>to you all:
>>>
>>>SUMMARY
>>>When considering a new, fairly complex, high density PCB design (defined
>>>often on the basis of how many and what pitch area array devices are
>>>required) with limited test probe access for ICT, the following
>>>considerations should be met:
>>>1) Ensure only highly qualified board fabrication capabilities are used.
>>>This must be done to provide printed circuitry that has the highest
>>>laminate
>>>integrity, hole quality and reliability, plated or coated surfaces that
>>>solder wet, and the ability to do adequate bare board testing in
>>>conjunction
>>>with effective X-Sectional analysis. This will prevent many other
defects
>>>during the assembly operation as poor quality solder joints, and shorts
or
>>>opens when hole walls fail.
>>>2) Ensure only highly qualified assembly capabilities are used. This
must
>>>be
>>>done to provide defect free assemblies with high quality and reliability
>>>solder joints, specified component placement and orientation, and the
>>>ability to prove all this with a well thought out test strategy.
>>>3) Ensure a well thought out test strategy is in place consisting of
some
>>>or
>>>all the following:
>>>?
>>>X-Ray used on all area array devices to ensure high quality solder
joints
>>>and the ability to reduce the number of test probe pins and test points
>>>relating to these device types.
>>>?
>>>AOI capabilities to determine solder joint quality for leaded and
discrete
>>>SMD?s as well as specified component types with proper orientations,
>>>polarity, and values. This too will minimize the number of test points
>>>required along with attendant bed of nails in those areas shown to meet
>>>specified requirements.
>>>?
>>>The use of boundary scan in those circuit areas deemed viable for such
>>>testing.
>>>With all the above, it is possible to create and implement a test
strategy
>>>capable of providing for all test requirements for our board types but
RF.
>>>I
>>>am studying a R/F test plan.
>>>
>>>
>>>Earl Moon
>>>
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