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July 2002

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Subject:
From:
Dave Hillman <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 16 Jul 2002 16:53:12 -0500
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Hi Werner! Terry is describing a HASS (highly accelerated stress screen) or
a HALT (highly accelerated life test) type of chamber. We have six of the
HASS chambers which are used to improve printed wiring assembly design
robustness (we track what fails, determine if that failure mode/mechanism
is valid for the use environment and make any appropriate design
improvements). These chambers can indeed provide temperature ramp rates of
5-50C per minute (they use LN2 boost) - the ultimate in thermal shock
recipes. I think you raised the most important questions - what is the
relationship of the failure modes/mechanisms induced by the HALT chamber
and the failure mechanisms the printed wiring assembly undergoes in its use
environment? Pretty tough question.

Dave Hillman
Rockwell Collins
[log in to unmask]




Werner Engelmaier <[log in to unmask]>@ipc.org> on 07/16/2002 07:25:49 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
       to [log in to unmask]

Sent by:    TechNet <[log in to unmask]>


To:    [log in to unmask]
cc:

Subject:    Re: [TN] Stress screening of multi layer production boards for
       optimum         reliability


Hi Terry,
>My thermal stressing uses the following parameters:
>10 cycles of hot / cold exposure in a HALT chamber,
>-60 deg C to +120 deg C temperature excursions,
>40 deg C per minute temperature ramp rate.
>The boards are electrically tested after thermal stressing.
A: The ramp rate surely is not correct. What exactly is a "HALT" chamber?
Depending on the nature of the failures you experience, your testing is not
much of an ESS, and electrically testing after, not during, thermal
stressing
will show little even if latent defects are precipitated to failure.
>I calculate the screening is using approximately 20% of the expected life
of
the
>assembled boards, so I am reluctant to increase the stress levels.
A: On the basis of what model do you make this calculation? You do nopt
even
have a failure mode, let alone a root-cause failure mechanis.
>My board manufacturer has made several process improvements over the last
year but
>I have not seen a significant improvement in my assembly yield.
A: Again. without knowing what is really happening, what the design details
are, and how these PCBs are used, it is impossible to make concrete
recommendations.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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