Hi, Terry,
We don't temp cycle PCB's ourselves before assembly - our fab house does
that for us prior to shipment, but I'm looking at your cycling figures.
The range is OK (-60 to +120), but - forgive the impertinance - do you
really mean a ramp rate of 40 degrees per minute? It's not a typo and
should have been 4 degrees per minute?
What material is your boards made from, and are they delivered to you, and
stored, in sealed bags with desiccant sachets to keep them dry? If they're
made from, say, FR4 and stored open to the atmosphere for a few weeks or
even months, they're probably full of absorbed moisture. If this isn't
baked out prior to thermal cycling (90 deg for about 6 hours), the rapid
cooling to minus 60 will freeze the moisture and cause delamination. The
rapid heating will thaw the ice, and the water will then be trying to
escape quickly as steam, possibly causing more delamination.
HALT is a pretty aggressive way of ESS testing production boards, and my
first reaction (in the absence of greater detail) is that you maybe not
finding weak boards, you're killing a few and weakening others.
Temperature cycling is not a bad way to check that PCB's are OK before
assembly, but I recommend you pre-bake them first as suggested above, then
cycle them gently. Use a 4 or 5 degrees per minute ramp rate with a
reasonable dwell time at top and bottom of each cycle for the boards to
stabilise - about 30 minutes should do it for unpopulated boards, and see
how things improve after that.
Peter (ex-BAE Systems)
Terry Exell <[log in to unmask]> 16/07/2002 02:45 PM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to Terry Exell
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: [TN] Stress screening of multi layer production boards for optimum
reliability
Dear All,
I am experiencing occasional open circuits on 16 layer boards during
assembly and
during in-service use. I have started thermal stressing all production
boards with
the aim of screening out any boards with latent defects and this is
identifying and
removing some problem boards. However, an equal number of problem boards
still
fail during assembly.
Does anyone use similar thermal stressing of production boards to help
improve
assembly yields and product reliability? If so, do you find it successful?
My thermal stressing uses the following parameters:
10 cycles of hot / cold exposure in a HALT chamber,
-60 deg C to +120 deg C temperature excursions,
40 deg C per minute temperature ramp rate.
The boards are electrically tested after thermal stressing.
I calculate the screening is using approximately 20% of the expected life
of the
assembled boards, so I am reluctant to increase the stress levels.
My board manufacturer has made several process improvements over the last
year but
I have not seen a significant improvement in my assembly yield.
Best regards
Terry Exell
PCB Assembly Engineer
BAE SYSTEMS
Plymouth, UK
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