Joyce:
I started in contract manufacturing and have moved into the design realm. I
agree that alot of designers need to see a production facility to straighten
their heads but the unfortunate situation is it is not feesable. A company
will not pay design engineering money to work in assembly, and unlike myself
who used it to work thru college, contract manufacturing does not pay enough
to sustain this engineering type. DFM is needed but always the
afterthought. My hands are dirty but I am also paying dearly for not taking
the fast track to Engineering. Welcome to the 21st century!!!
Ken
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of joyce
Sent: Tuesday, July 02, 2002 8:18 AM
To: [log in to unmask]
Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
"some young Design
>Engineers don't take DFM seriously".
if someone don't know "manufacturing", never set a foot into the manufacture
floor, asking DFM is very un-reasonable. Send them to the floor for 6
month, you will see the difference. Send them to repair shop for another 6
month, you will get your DFR (design for reliability). In the process, you
will get rid of the one who do not want to get their hands dirty too.
jk ;-0
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]]On Behalf Of Ingemar Hernefjord
>(EMW)
>Sent: Tuesday, July 02, 2002 5:13 AM
>To: [log in to unmask]
>Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>
>
>So, so, don't weep dear Peter,
>next line may comfort you a little
>Production engineers are not included, what we mean are Design
>Engineers...woe, woe...now I'll get that beeswarm on myself instead...
>Like your humoristic spirit, Peter...
>
>Severily: DFM is like star of Betlehem, we too try to walk
>steadily in that direction.Unfortunately, some young Design
>Engineers don't take DFM seriously.
>
>Ingemar
>
>
>
>
>-----Original Message-----
>From: [log in to unmask] [mailto:[log in to unmask]]
>Sent: den 2 juli 2002 10:11
>To: TechNet E-Mail Forum.; Ingemar Hernefjord (EMW)
>Cc: [log in to unmask]
>Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>
>
>
>Dear Ingemar,
>
>I am deeply hurt! (sulk!) What's wrong with us Production Engineers, eh? We
>have to make all this hardware so that it works, and it's important that we
>have an input to board design. Maybe you're actually a wee Viking devil,
>sitting on Earl's left shoulder, tempting him away from the true path of
>DFM!?
>
>Peter
>
>
>
>"Ingemar Hernefjord (EMW)" <[log in to unmask]>
>02/07/2002 02:49 PM
>Sent by: TechNet <[log in to unmask]>
>
>Please respond to "TechNet E-Mail Forum."; Please respond to "Ingemar
>Hernefjord (EMW)"
>
> To: [log in to unmask]
> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
> Subject: Re: [TN] FAULT/DEFECT TEST STRATEGY
>
>
>
>
>
>
>
>
>Hi Earl,
>you seem to cover most in those few lines
>I would add this first thing I did: use only highly skilled operators
>(unless you see 'capabilities' below as human resources). Best guarantee,
>better than good engineers....gosh...I'll be in bad situation now...
>Best regards
>Ingemar Hernefjord
>PS. unwritten rule here : never let in an engineer in the production! Bit
>of black humour, but with great deal of truth.
>
>-----Original Message-----
>From: Earl Moon [mailto:[log in to unmask]]
>Sent: den 1 juli 2002 19:14
>To: [log in to unmask]
>Subject: [TN] FAULT/DEFECT TEST STRATEGY
>
>
>Folks,
>
>I am not a test engineer but having to do catch up quickly to develop a
>sensible test strategy to find faults and/or defects usin a combination of
>test disciplines and elements. Watched my board designer spend a very long
>time placing 1800 test points, some not on grid, as something of an
>experiment on a non-HDI, but approaching it, and didn't like the results.
>
>I'm hoping some of you can offer positive, or negative, criticism
>concerning
>the following summary I've come up with though probably not new to you all:
>
>SUMMARY
>When considering a new, fairly complex, high density PCB design (defined
>often on the basis of how many and what pitch area array devices are
>required) with limited test probe access for ICT, the following
>considerations should be met:
>1) Ensure only highly qualified board fabrication capabilities are used.
>This must be done to provide printed circuitry that has the highest
>laminate
>integrity, hole quality and reliability, plated or coated surfaces that
>solder wet, and the ability to do adequate bare board testing in
>conjunction
>with effective X-Sectional analysis. This will prevent many other defects
>during the assembly operation as poor quality solder joints, and shorts or
>opens when hole walls fail.
>2) Ensure only highly qualified assembly capabilities are used. This must
>be
>done to provide defect free assemblies with high quality and reliability
>solder joints, specified component placement and orientation, and the
>ability to prove all this with a well thought out test strategy.
>3) Ensure a well thought out test strategy is in place consisting of some
>or
>all the following:
>?
>X-Ray used on all area array devices to ensure high quality solder joints
>and the ability to reduce the number of test probe pins and test points
>relating to these device types.
>?
>AOI capabilities to determine solder joint quality for leaded and discrete
>SMD?s as well as specified component types with proper orientations,
>polarity, and values. This too will minimize the number of test points
>required along with attendant bed of nails in those areas shown to meet
>specified requirements.
>?
>The use of boundary scan in those circuit areas deemed viable for such
>testing.
>With all the above, it is possible to create and implement a test strategy
>capable of providing for all test requirements for our board types but RF.
>I
>am studying a R/F test plan.
>
>
>Earl Moon
>
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