Hi Terry,
>My thermal stressing uses the following parameters:
>10 cycles of hot / cold exposure in a HALT chamber,
>-60 deg C to +120 deg C temperature excursions,
>40 deg C per minute temperature ramp rate.
>The boards are electrically tested after thermal stressing.
A: The ramp rate surely is not correct. What exactly is a "HALT" chamber?
Depending on the nature of the failures you experience, your testing is not
much of an ESS, and electrically testing after, not during, thermal stressing
will show little even if latent defects are precipitated to failure.
>I calculate the screening is using approximately 20% of the expected life of
the
>assembled boards, so I am reluctant to increase the stress levels.
A: On the basis of what model do you make this calculation? You do nopt even
have a failure mode, let alone a root-cause failure mechanis.
>My board manufacturer has made several process improvements over the last
year but
>I have not seen a significant improvement in my assembly yield.
A: Again. without knowing what is really happening, what the design details
are, and how these PCBs are used, it is impossible to make concrete
recommendations.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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