Thanks Eddie,

now I see what you mean.

My conclusion is that some CE must be done when considering this kind of
job, the PCB designer shall concur with the board house. Under these
circumstances, some  designs are doable, at no extra charge.

Thanks to all who answered,
Ioan

> -----Original Message-----
> From: Eddie Rocha [SMTP:[log in to unmask]]
> Sent: Wednesday, May 01, 2002 8:12 PM
> To:   TechNet E-Mail Forum.; Tempea, Ioan
> Subject:      Re: [TN] Flip-flop panels
>
> Don't do it unless, you understand it thoroughly. Again it's the
> multilayer stack-up that complicates things for example:
>       diel         diel          diel         diel         diel
> L1 - 5.0 - L2 -14.0 - L3 - 5.0 - L4 - 5.0 - L5 - 5.0 - L6  flipped
>
> L6 - 5.0 - L5 - 14.0 - L4 - 5.0 - L3 - 5.0 - L2 - 5.0 - L1  flopped
>
> you can see that the dielectric spacing between layers 2 & 3 in the
> flipped version is 14 mils but the flopped version it's 5 mils. I hope
> this explains it

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