Hi, All,
Although punching via holes for BGA's right through a board can lead to
that nice sagging effect by considerably weakening the BGA area, using
blind vias leaves you without anywhere to probe when doing diagnostics and
trouble shooting. How do other hi-rel guys and gals get round the test
probing issue if using blind vias? ICT boundary scanning? Is that good
enough, or does it require some very slick DFT?
I guess with BGA packages getting ever smaller, there's no room for offset
vias in some applications, so v-i-p is the only option. For hi-rel boards,
I would silver epoxy fill them, plate over them and mount BGA's as normal.
I wouldn't advocate tenting of any kind for hi-rel applications because of
what can be trapped inside.
Peter
fullname
<[log in to unmask] To: [log in to unmask]
ORG.SG> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Vias in pads
<[log in to unmask]
ORG>
04/05/02
07:58 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
fullname
I personally believe that blind v-i-p is a good technique especially for
BGA as it free up the channel
for routing. Through v-i-p no matter which package you used will still wick
off the solder from your
joint, that is obvious..
It is also obvious that as board get denser each day, micro via will be
used and so will it be blind.
Much has been discussed about micro via, blind via, especially via in pads.
It is a matter of how we
become more innovative to combine the technique and process to make it
better.
I have always wonder whether someone have actually do a study to look into
the correlation between the
volume of solder paste, various blind via diameter and the type of blind
via (Type 1 & II HDI), etc. I
am sure from such study, the process engineer would able to advise should
v-i-p be used, with the voulme
of solder paste can be determine - leading to a good and reliable solder
joint, etc.
Is that my fancy idea or in actual fact work have been done? If the latter
is yes, I would appreciate
you can share it with me.
Just my 1 cent worth.
Regards - Wee Mei
"Maddox, Allen T" wrote:
> Like I said before, we're going through this now. It seems that the EMI
> gurus are preaching to Engineers to put the via in the pad. This is
> something that we, as designers, are going to have to figure out how to
deal
> with. It's a challenge and goes against everything I've learned over the
> years But, if the board doesn't work it doesn't make a difference how
> manufacturable it is. There has got to be a way to make everybody happy.
Do
> we have to go to blind micro Vias?
>
> Allen M.
>
> -----Original Message-----
> From: Mark Charlton [mailto:[log in to unmask]]
> Sent: Thursday, April 04, 2002 7:40 AM
> To: [log in to unmask]
> Subject: Re: [TN] Vias in pads
>
> Steve,
>
> We're concerned about the solder wicking through to the other side and
> presenting "balls" of solder on the second side. This is a 120mil thick
PCB
> and would take a bunch of extra print strokes to fil the via, then the
> stencil won't gasket and would probably be damaged when printing second
> side, damage by squeege blades. I like the prevailing opinion: REDESIGN.
>
> Mark
>
> -----Original Message-----
> From: [log in to unmask] [mailto:[log in to unmask]]
> Sent: Wednesday, April 03, 2002 7:06 PM
> To: [log in to unmask]
> Subject: Re: Vias in pads
>
> Hi Mark,
>
> I hope you've seen my pictures and seen what happened with me. But
something
> you might try that I didn't think of when I ran my ten boards, is to do a
> double print stroke when printing the board...this may "force" some of
the
> paste down inside the via and give it a bit of additional paste to fill
down
> inside the via so that it doesn't suck so much from the fillet... maybe
> worth a try.
>
> -Steve Gregory-
>
> Group,
>
> I have a challenging assembly that I need some of your combined
professional
> experience to resolve.
>
> I have been presented a 120mil-thick polyamide (sp?) dbl-sided PCB, gold
> finish with the majority of the C's&R's being 0402's, some 20mil QSOP and
> TSOP, QFP. That's somewhat challenging in itself but to compound
matters,
> there are MANY instances of vias in the SMT pads. The vias go through
the
> PCB and are NOT tented/plugged. Many of these vias are on only one side
of
> 2-terminal parts. I don't have the complete set of gerbers and drill
> drawing so I can't determine the drill size of these vias.
>
> Is there ANYTHING I can do at this stage of the game to produce a quality
> product in terms of stencil design, reflow profile, etc? The customer is
> aware of the potential problems this presents. Their primary concern is
the
> solder wicking through to the other side. Mine too, in addition to
> solder-starving and tomb stoning.
>
> Your thoughts are appreciated. Oh yeah, of course it's R/F.
>
> Mark Charlton
> Engineering Manager
> MSI of Central Florida, Inc.
> 7703 Technology Drive Ste. 102
> Melbourne, FL 32904
> (321) 725-0626 x.24
> (321) 725-0627 fax
> [log in to unmask]
>
>
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