Steve,
I haven't seen a photo showing your board and component layout but may guess is that you have "Double Reflow". I hate the name the "Double Reflow" name IBM Austin coined in their Nepcon 1994 presentation but it has sort of stuck. Check out the following two references:
Hallmark, Clay et.al., Nepcon West 1994 "Double Reflow: Degrading Fine Pitch Joints In The Wave Soldering Process
Wenger, George et. al., SMI 1995 "Double Reflow: The Stress Fracture Reliability Problem of the 90's"
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: Cyker, Howard A (Howie) [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 11:09 AM
To: [log in to unmask]
Subject: Re: [TN] Secondary reflow over wave...
Steve,
We have also seen this before. The cause was secondary reflow in most
cases, and required "tweaking" of the wave profile. If that's not
successful, then you may require a selective wave fixture, however that may
not be possible due to your board layout.
You said that ". . . every pad has a via, they alternate . . ." Are you
saying you have VIP (via in pad)? If yes, what size are the vias, and are
you also seeing solder being scavenged through the vias?
Howard A. Cyker
Lucent Technologies
New Product Engineering
Email [log in to unmask]
Phone 978-960-2964
-----Original Message-----
From: Jorge Santana [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 10:35 AM
To: [log in to unmask]
Subject: Re: [TN] Secondary reflow over wave...
Steve
We have seen this on a SOIC that has coplanarity issue on the leads and
the problem was caught at wave solder when the part reflowed at top side of
the board leaving one open junction at the lead.
I have seen this also at BGA and we used Kapton tape to mask.
Thanks
Jorge Santana
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Monday, April 22, 2002 8:07 PM
To: [log in to unmask]
Subject: [TN] Secondary reflow over wave...
Hi All!
Got a situation here that I think is secondary reflow...
Have a board here that has some J-leaded DRAM that in functional test, they
can get the board to pass test by putting some pressure on top of some of
the
40-pin J-leaded DRAM's that are causing them to fail...
Out of SMT things look fine, but I have observed some boards that have
failed, show an unusual solder joint appearance after wave. The board is
"swiss-cheesed" with vias, and none of them are tented. Every pad has a via,
they alternate, some have .050" traces to the pad, some have .020" traces to
the pad.
Where we're seeing problems is where there is a bank of them (like a grid of
2 by 8 of them layed-out side by side).
I'm thinking secondary reflow because of the open vias...or could be CTE
mis-match between the part and the board. It's a .062" FR4 board, with
fairly
large 40-pin SOJ's, could be experiencing some hellacious mismatch, no? The
gull-wing parts we don't see the problem, even though the via placement is
the same standard as with the J-leaded parts...J-leads aren't as compliant?
Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded parts
to
learn what it is seeing...will tell me a lot...
Just wondering if anybody else has run into this before...
-Steve Gregory-
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