Hi All!

Got a situation here that I think is secondary reflow...

Have a board here that has some J-leaded DRAM that in functional test, they
can get the board to pass test by putting some pressure on top of some of the
40-pin J-leaded DRAM's that are causing them to fail...

Out of SMT things look fine, but I have observed some boards that have
failed, show an unusual solder joint appearance after wave. The board is
"swiss-cheesed" with vias, and none of them are tented. Every pad has a via,
they alternate, some have .050" traces to the pad, some have .020" traces to
the pad.

Where we're seeing problems is where there is a bank of them (like a grid of
2 by 8 of them layed-out side by side).

I'm thinking secondary reflow because of the open vias...or could be CTE
mis-match between the part and the board. It's a .062" FR4 board, with fairly
large 40-pin SOJ's, could be experiencing some hellacious mismatch, no? The
gull-wing parts we don't see the problem, even though the via placement is
the same standard as with the J-leaded parts...J-leads aren't as compliant?

Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded parts to
learn what it is seeing...will tell me a lot...

Just wondering if anybody else has run into this before...

-Steve Gregory-

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