One more cent's worth is to enhance the board's own built-in test (BIT)
capability, wich reduces the amount of ICT tesing required.
Peter
Lucas
Paul-R32425 To: [log in to unmask]
<Paul.Lucas@MOT cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
OROLA.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] Circuit Test
TechNet
<[log in to unmask]
G>
02/27/02 02:17
AM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to Lucas
Paul-R32425
Alan,
We too have the same situation as you do in regards to ICT of complex
PWA's. Our design engineers have not included test points, wide traces or
anything else that would allow for the in circuit testing of our boards.
Our boards are very dense in component population and use a mixture of fine
pitch, SMD and thru hole components on them. They are 10"X18" boards that
have 8 to 12 layers. As big as they are there is just no room to fit any
test points on there. That's ok because, the designers have no intentions
of going back and re-routing the boards to allow for this.
So we have had to compensate by finding an assembly house that has AOI.
They do 100% inspection on every board they assemble. When we receive the
boards we add several more components by hand and then we do a visual
inspection. After that we use a meter or curve tracer to check the power
planes for shorts between them and ground. Finally comes what we call the
"smoke test". This is were the board is plugged into a test chassis and
turned on. You will soon find out if you still have any shorts are reversed
components that you missed. Believe it or not this has been successful for
us in getting boards built and working. ICT is obviously much faster in
testing the boards, but not always more accurate or successful(Test
programs are never complete and constantly changing). One of the big reason
this works for us is because we have low volumes and a high mix(ICT is
expensive for low volume, very complex boards).
You have to balance the cost of adding ICT into your designs and to your
assembly costs against the cost of visual inspection and more labor
intensive test procedures. For us it was about the same cost and the
quality has not suffered by omitting ICT.
Hope this helps,
Paul
-----Original Message-----
From: Keach Sasamori [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 8:21 AM
To: [log in to unmask]
Subject: [TN] Circuit Test
Forwarding for Alan Groves:
>>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
Hi, I have not used the forum before but am currently at the centre of an
internal company clash, and would appreciate any help on the issue below.
My problem involves In Circuit Test ;-
Our Logistics department here (which includes production, test and
deployment) are demanding quite strongly that ICT be done on each PWB we
design, and that every signal and every component value be tested, i.e.
100%
test point access on traces (even N/Cs).
The Engineers are not quite so keen as most have used JTAG and Boundary
scan
etc to evaluate the devices they deem critical. They are also worried (and
rightly so) about the effect that test points may have on traces with
controlled impedance, or those on critical timing paths, but are not
adverse
to giving test point access where possible and where the design will not be
affected.
The boards we design here are also very complex, we mount SMDs on both
sides
and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
boards are also very dense with real estate at an absolute priority such
that we use the smallest devices available. Currently we have 0,8mm pitch
uBGAs whose routing must be resolved vertically, i.e. blind and buried
vias,
with obvious drawbacks for ICT.
We have in the past used the Specctra autorouter to allocate test point
access but the best result so far is about 80% (of course I could use bad
placement to improve this!), and even here we used the smallest possible
access points 0.03" on the smallest possible grid 0.05". On some boards it
is below 50% access. Our usual via holes only have land of 0.024", so these
cannot be used.
I could of course try to manually allocate access points, by increasing via
land where appropriate, or thickening and exposing traces where possible
and
deploying all other tricks I can, but the time and effort here would be
enormous, and other projects may suffer as a result.
Any advise or knowledge that can be offered here would be most welcome.
Is this problem common to other companies?
How is the Industry thinking about ICT at the moment?
Are there better autorouters?
Are there ICT houses that can use smaller nodes on tighter grids?
Is there new technology just around the corner?
Etc Etc.
With many thanks in advance, and regards,
Alan Groves CID,
Technical Services (D.O.) Team Leader.
Spectel , 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
Or Via :
Spectel, Inc.
200 Minuteman Road
Andover, Massachusetts 01810 USA
PH: 1.978.552.6260
FX: 1.978.552.6250
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