Alan,
You have my heartfelt sympathy, and I can only help relieve a tiny portion
of what you're asking, as I'm a Jack of all Trades and Master of the
Inverse.
There are various techniques for grouping and isolating components in a
layout such that they can be tested with fewer test points. The pad sizes
and spaces you quote are at the limit from what I know, but I understand
that probe technology is having to improve all the time to keep pace with
ever-developing miniaturisation. I suggest you talk closely to Agilence, or
similar ICT tester experts to see what they have to say. And don't
necessarily listen too hard to what the jig manufacturers have to say. The
ICT test machine manufacturers will tell you what it's possible to test and
how. All you have to do then is find a jig manufacturer who can comply.
Only relax your requirements as you beat a strategic retreat from the
apparently impossible to the just possible.
Another two cents' worth is - we also have densely populated, double-sided,
12 layer boards, and we opted to manually route them. We couldn't rely on
any autorouter to efficiently route a board and maintain our design rules,
as we wound up with critical traces being routed all over the place and via
a number of layers instead of being 'as short as possible' and limited to
one layer. Manual routing gave us infinitely more control over what was
routed where, and it didn't change out of all recognition with every minor
amendment. It takes longer and is possible to prone to at least the same
number of errors (albeit human rather than machine), but it worked better
for us when laying out how many ICT pads we really needed and where they
should go.
FYI, The routers we s/c to use PADS, Allegro or Mentor, each at latest
versions, which, when comparing results, is a good spread of routing
software in terms of quality.
Peter
ST Aero
Keach
Sasamori To: [log in to unmask]
<KeachSasamor cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
[log in to unmask]> Aero/ST Group)
Sent by: Subject: [TN] Circuit Test
TechNet
<[log in to unmask]
ORG>
02/26/02
11:21 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Keach
Sasamori
Forwarding for Alan Groves:
>>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
Hi, I have not used the forum before but am currently at the centre of an
internal company clash, and would appreciate any help on the issue below.
My problem involves In Circuit Test ;-
Our Logistics department here (which includes production, test and
deployment) are demanding quite strongly that ICT be done on each PWB we
design, and that every signal and every component value be tested, i.e.
100%
test point access on traces (even N/Cs).
The Engineers are not quite so keen as most have used JTAG and Boundary
scan
etc to evaluate the devices they deem critical. They are also worried (and
rightly so) about the effect that test points may have on traces with
controlled impedance, or those on critical timing paths, but are not
adverse
to giving test point access where possible and where the design will not be
affected.
The boards we design here are also very complex, we mount SMDs on both
sides
and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
boards are also very dense with real estate at an absolute priority such
that we use the smallest devices available. Currently we have 0,8mm pitch
uBGAs whose routing must be resolved vertically, i.e. blind and buried
vias,
with obvious drawbacks for ICT.
We have in the past used the Specctra autorouter to allocate test point
access but the best result so far is about 80% (of course I could use bad
placement to improve this!), and even here we used the smallest possible
access points 0.03" on the smallest possible grid 0.05". On some boards it
is below 50% access. Our usual via holes only have land of 0.024", so these
cannot be used.
I could of course try to manually allocate access points, by increasing via
land where appropriate, or thickening and exposing traces where possible
and
deploying all other tricks I can, but the time and effort here would be
enormous, and other projects may suffer as a result.
Any advise or knowledge that can be offered here would be most welcome.
Is this problem common to other companies?
How is the Industry thinking about ICT at the moment?
Are there better autorouters?
Are there ICT houses that can use smaller nodes on tighter grids?
Is there new technology just around the corner?
Etc Etc.
With many thanks in advance, and regards,
Alan Groves CID,
Technical Services (D.O.) Team Leader.
Spectel , 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
Or Via :
Spectel, Inc.
200 Minuteman Road
Andover, Massachusetts 01810 USA
PH: 1.978.552.6260
FX: 1.978.552.6250
---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
SET Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
---------------------------------------------------------------------------------
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------
|
