I have also faced "requirements" like this several times. Though is
achievable on lower complexity products, it is typically not possible for
the type of boards you describe. Your boards are the specific test scenario
that led the industry to develop boundary scan test methods and the JTAG
interface. They were invented to give visibility to buried or otherwise
unreachable nodes, thus making higher density products feasible. They did
not come about to make test development easy.
It sounds like your Logistics Group is simplifying their own life and
covering their collective posterior at everyone else's expense. This kind
of mindset is similar to requiring that every component specified has
multiple manufacturers and be in stock at multiple distributors. While
these are laudable goals, if you take these as requirements, you will design
products that are easily manufactured and tested but are too large or
technologically backward for the end use, i.e. they won't sell.
This is a tough nut to crack because 100% test access is not a requirement
for assuring a conforming, quality product. It is a requirement for
enabling someone to do their job without thinking. Being conservative and
insisting on processes that you can stand behind is a reasonable starting
point. When it precludes your achieving customer requirements, it's time
for _them_ to come up with some alternatives.
Complex, dense boards are challenging to create a test strategy for and
there is no avoiding it, at least with today's test technologies. You will
likely have to use a combination of technologies to fully test your product.
The SPECCTRA router is a very capable design tool and there is no magic
bullet here. IMHO, double-sided 12-layer boards and 100% test access are
incompatible.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Keach Sasamori
> Sent: Tuesday, February 26, 2002 9:21 AM
> To: [log in to unmask]
> Subject: [TN] Circuit Test
>
>
> Forwarding for Alan Groves:
>
> >>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
> Hi, I have not used the forum before but am currently at the centre of an
> internal company clash, and would appreciate any help on the issue below.
>
> My problem involves In Circuit Test ;-
> Our Logistics department here (which includes production, test and
> deployment) are demanding quite strongly that ICT be done on each PWB we
> design, and that every signal and every component value be
> tested, i.e. 100%
> test point access on traces (even N/Cs).
> The Engineers are not quite so keen as most have used JTAG and
> Boundary scan
> etc to evaluate the devices they deem critical. They are also worried (and
> rightly so) about the effect that test points may have on traces with
> controlled impedance, or those on critical timing paths, but are
> not adverse
> to giving test point access where possible and where the design
> will not be
> affected.
> The boards we design here are also very complex, we mount SMDs on
> both sides
> and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
> boards are also very dense with real estate at an absolute priority such
> that we use the smallest devices available. Currently we have 0,8mm pitch
> uBGAs whose routing must be resolved vertically, i.e. blind and
> buried vias,
> with obvious drawbacks for ICT.
> We have in the past used the Specctra autorouter to allocate test point
> access but the best result so far is about 80% (of course I could use bad
> placement to improve this!), and even here we used the smallest possible
> access points 0.03" on the smallest possible grid 0.05". On some boards it
> is below 50% access. Our usual via holes only have land of
> 0.024", so these
> cannot be used.
> I could of course try to manually allocate access points, by
> increasing via
> land where appropriate, or thickening and exposing traces where
> possible and
> deploying all other tricks I can, but the time and effort here would be
> enormous, and other projects may suffer as a result.
>
> Any advise or knowledge that can be offered here would be most welcome.
> Is this problem common to other companies?
> How is the Industry thinking about ICT at the moment?
> Are there better autorouters?
> Are there ICT houses that can use smaller nodes on tighter grids?
> Is there new technology just around the corner?
> Etc Etc.
>
> With many thanks in advance, and regards,
>
> Alan Groves CID,
> Technical Services (D.O.) Team Leader.
> Spectel , 21 Stillorgan Ind. Park, Stillorgan,
> Co. Dublin. Ireland.
> Phone: 353 907 62803
> Fax: 353 1 2953740
> Email: [log in to unmask]
> Internet: www.spectel.com
>
> Or Via :
> Spectel, Inc.
> 200 Minuteman Road
> Andover, Massachusetts 01810 USA
> PH: 1.978.552.6260
> FX: 1.978.552.6250
>
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