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February 2002

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Subject:
From:
"McMullen, Kerry" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 20 Feb 2002 12:44:44 -0500
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Hi Richard,
If you send me the recommended footprints, I can give you some general
advice in the Pick and Place / In Circuit Test Pad design.  We have done a
few duals, but I try to "prohibit" them as you use up board real estate very
quickly.
Kerry

-----Original Message-----
From: Richard Hawkins [mailto:[log in to unmask]]
Sent: Wednesday, February 20, 2002 11:57 AM
To: [log in to unmask]
Subject: [TN] pads for so package and sop package?


I have a situation in which my company wishes to "dual source" an IC, the
only catch is that one is an so package and the other is a sop package.

This is a new problem for me.  I am looking to the experience and expertise
of this list to help me come to the correct answer for my company.

Any advise/opinion/experience will be appreciated.

TIA

Sincerely,


Richard Hawkins

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