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February 2002

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Subject:
From:
tony steinke <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Mon, 4 Feb 2002 10:20:26 -0800
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text/plain (70 lines)
Daan,

If you specify the final etched dimensions on your print, that should
supercede any IPC tolerances, and if your board supplier has a
problem with those tolerances or notes then contact should be made
by supplier for a deviation. Assuming that the board is being built with
half ounce copper foil on the outer layers, your supplier should not have
problems with maintaining +/-1 mil on a 12 mil surface mount pad.

Tony Steinke
tsteinke@ait-atlanta
----- Original Message -----
From: d. terstegge <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, February 04, 2002 2:33 AM
Subject: [TN] Tolerance on padwidth


Hi Technet,

IPC-6012 mentions "when not specified on the master drawing the minimum
conductor width shall be 80% of the the conductor pattern supplied in the
procurement documentation".
This is fine for the tracks, but it may cause problems with the solderpads.
Quite often I see that the 12 mil designed fine-pitch pads have a width of
only 9.6 mil on the actual products, leaving a marginal process window for
assembly.
I can live with 11 mil instead of 12 mil, but 9.6 mil is too small for my
taste. The questions:
1)   Is there an additional specification for the etching tolerance of the
solderpads ?
2)   If we put additional requirements on the master drawing, what would be
an acceptable value ?

As always I'm very interested to hear your comments,

Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net

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