Good Morning Technetters,

For Technechters who celebrate Chinese New Year: Happy
New Year!

After reviewing a few panel drawing from different
memory manufacture(of step and repeat image) I realize
that their tolerance (non-accumulative) are 5 mils.
In order words, the step and repeat image measure3d
from PCB fiducials are not to exceed 5 mils; and
tolerance are not accumulative.

Some they don't even state it out but they assume that
the boardhouse follow the tolerance of their panel
drawing dimension.

As the design for memory module becomes more and more
complicated (16 mils pitch, Micro BGA, stack for 20
mils pitch components), the 5 mils tolerance become a
serious issue for SMT process.  Imagine that the
stencil house offset 3 mils to one side and the
boardhouse offset 3 mils or even 4 mils to another
side, then what would happen to the SMT manufacture?

I dont know if any IPC member have ever created any
document for the panel drawing or do we have any
existing or pre-define tolerance for this matter?

Please advice.

Thanks,

Stacy


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