I'm wondering whether this problem is related to the etched trace geometry.
Trace geometry can vary greatly depending on the process used to build the
board and the surface finish. Just take a look at IPC 600 3.2.1 and IPC
2221 Section 10 (Table 10-3). It shows this very well. No matter the
geometry though, the effective width from IPC is the same, the widest part
of the trace. On some boards this can be the top of the trace and on others
it can be the bottom. If the board retains the etch mask, typically
electrolytic nickel/gold, the top will be the widest. But if the etch mask
is stripped any of a variety of surface finishes (HASL, ENIG, ImAg, OSP
etc) are used, the top likely will not be the widest part.
Since SMT uses the top of the pads, it's not too far-fetched to see that a
pad that would have 12 mil top with electrolytic nickel gold but only 10
mils or less with ENIG and BOTH products would meet IPC specs for effective
width. IPC 600 and 2221 even points this out. There's a note in each that
says "The different etch configurations may not meet intended design
requirements."
So what do you do. Make sure you understand how your fabricator builds the
board, the impact of the surface finish on pad geometry and what shape you
need. One question to ask your fabricator is do they treat the outer layer
artwork differently if the board is electrolytic or electroless nickel/gold.
They should because they two surface finishes will yield a very different
trace and pad geometry.
Finally, if the SMT pad width is critical, you can specify that the top of
the pad must meet a specified width regardless of the IPC specified
conductor width.
> ----------
> From: [log in to unmask][SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;[log in to unmask]
> Sent: Tuesday, February 05, 2002 2:15 AM
> To: [log in to unmask]
> Subject: Re: [TN] Tolerance on padwidth
>
> Hi, Daan,
>
> The old MIL-PRF-55110 permitted a reduction of up to 20% on the minimum
> conductor pattern width for etching roughness, pin holes, etc. This is
> bang
> on the 12 mils to 9.6 mils reduction you're uncomfortable with, and I
> would
> be too.
>
> I used a fab house once that ADDED this 20% to the designed width so they
> could lose it later in their processing - result was that the conductors
> ended up too wide and the spacing between too narrow. Another fab house
> managed to reduce some pad widths to half of what they should have been
> because of uneven copper plating. All were rejected.
>
> Don't have my IPC spec to hand to see what that says, but I remember it
> being much stricter in its requirements.
>
> Peter
>
>
>
>
> "d. terstegge"
> <[log in to unmask] To:
> [log in to unmask]
> GROUP.COM> cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> Sent by: TechNet Aero/ST Group)
> <[log in to unmask]> Subject: [TN]
> Tolerance on padwidth
>
>
> 02/04/02 06:33 PM
> Please respond to
> "TechNet E-Mail Forum.";
> Please respond to "d.
> terstegge"
>
>
>
>
>
>
> Hi Technet,
>
> IPC-6012 mentions "when not specified on the master drawing the minimum
> conductor width shall be 80% of the the conductor pattern supplied in the
> procurement documentation".
> This is fine for the tracks, but it may cause problems with the
> solderpads.
> Quite often I see that the 12 mil designed fine-pitch pads have a width of
> only 9.6 mil on the actual products, leaving a marginal process window for
> assembly.
> I can live with 11 mil instead of 12 mil, but 9.6 mil is too small for my
> taste. The questions:
> 1) Is there an additional specification for the etching tolerance of the
> solderpads ?
> 2) If we put additional requirements on the master drawing, what would
> be
> an acceptable value ?
>
> As always I'm very interested to hear your comments,
>
> Daan Terstegge
> SMT Centre
> Thales Communications
> Unclassified mail
> Personal Website: http://www.smtinfo.net
>
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