Earl,
It's worse than just using the test equipment guidelines. Along with that,
you have to deal with each of the test fixture makers' preferences as well.
What this boils down to is a negotiation with each CM's test engineering
group as to what is testable. They are not even slightly embarrassed asking
for 100% bottom side only coverage with 0.040" square test pads on 0.100"
centers (on a grid, of course) for a board with 6/6 mil line/space, 8/18 mil
via hole/pad and 0.8mm BGA's. I guess it's a good bargaining tactic, but
I'd like to think we're at least on the same team. Those are the same ICT
rules we were using fifteen years ago. But typical PCB design rules have
shrunk considerably during that time.
Lately, I've had reasonable luck arguing for the first two of the three
following design rules (all test pads are round):
nail size test pad dia. center-to-center
--------- ------------- ----------------
0.100" 0.035" 0.085"
0.075" 0.035" 0.057"
0.050" 0.025" 0.044"
To get the third rule, which is the one you really need on a high-density
board, be prepared for battle. From what I'm told, the problem is that the
50 mil test nails are fragile, and for the closer center-to-center spacings,
they can't be socketed. So when they wear out or bend, the test engineer
has to carefully replace a press-fit test nail. My basic response to this
serious problem is "So what", but NEVER SAY THIS or you will be testing the
boards yourself!
There is also the approximately 0.200" border required for the vacuum test
fixture seal. One shop I work with has mostly changed from vacuum fixtures
to over-clamped fixtures. It avoids the problems with leaky gaskets and
vias and gives the border space back to the PCB. The fixture does cost a
bit more but it is a minimal one-time cost. Most CM's I have worked with do
prefer the vacuum fixtures, so I assume there is a throughput difference,
but I don't know.
Are there any test engineers out there who can comment on whether the above
ICT design rules are typical for fixture fabricators today? Are the smaller
test nails and pads really that much more expensive and troublesome?
Sometimes I can allocate more board area for testing. However, in many
cases, increasing board area is not an option so we either give up test
coverage, rework the circuit to reduce components or use clamshell fixtures.
In these cases, I usually feel the trade off was not cost effective, but as
the circuit designer, I don't have all the information.
I didn't really mean to rant, but it's all over now.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------
|
