Vias may rob adjacent SJ if not masked.

That's the only justifiable beef I've had that forces masking. Unmasked vias
are just artifacts of CAD SW, unless used for ICT points.

RL

----- Original Message -----
From: Paul Truit <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 22, 2002 9:10 AM
Subject: [TN] Solder fill of via's and reliability


> I am interested in hearing others views in regard to allowing the wave
> soldering process to fill the vias with solder or tenting the vias with
> soldermask and how this relates to reliability.
>
> I am seeing more and more designs with the vias covered.  Wouldn't
> allowing the vias to fill with solder increase the reliability of the
> PCA?  Or is this a matter of covering for the "sins" of the bare board
> manufacturer's plating process?  Expecting .001" but getting
> .0007-.0008" copper plating.
>
> Should via's be left uncovered?
>
> Respectfully
>
> Paul
>
>
> --
> Paul Truit, Mfg. Eng.
> RBB Systems, Inc.
> 4265C E. Lincolnway
> Wooster, OH  44691
> Ph. (330) 567-2906 ext 514
> Fax (330) 263-5324
> Email: [log in to unmask]
>
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