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January 2002

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Subject:
From:
"Sauer, Steven T." <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 22 Jan 2002 14:02:57 -0500
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Hi Paul,
Years ago, the military high reliability soldering standards required PTHs
to be filled with a solder plug (wave soldered only, 25% recession
acceptable) or wire (swaged stud or clinched "C" or "Z" form) soldered in
the holes of type of 2 and 3 printed wiring boards.
After extensive testing and evaluation (data was also presented to the
military folks by industry), it was determined that the via holes could be
left unsoldered without compromising reliability of the interconnection.
The one drawback is partial fill of these via holes, when subjected to
stress and strain, the forces imparted on the PTH structure are not equally
distributed.  As such, this can cause the PTH to fail prematurely.  As such,
it is better to either fully fill the hole or leave the hold unfilled.
With respect to tenting of vias, I look at the following factors:
        gasketing during in-circuit testing
        minimize the amount of exposed conductive circuitry
                - shorting potential
                - cleaning challenges
In light of the above, it all depends on your end item application and
environment.  If you're worried about the reliability of your holes with
respect to wall thickness, I would specify what you want to your supplier
and then verify.  As Moonman says, "specify, verify and never trust".  The
only time that I would leave PTHs uncovered would be for test purposes, but
I would normally specify pads/targets for test points.

Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron

-----Original Message-----
I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.

I am seeing more and more designs with the vias covered.  Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA?  Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process?  Expecting .001" but getting
.0007-.0008" copper plating.

Should via's be left uncovered?

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