TECHNET Archives

January 2002

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Paul Truit <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 22 Jan 2002 12:10:54 -0500
Content-Type:
text/plain
Parts/Attachments:
text/plain (37 lines)
I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.

I am seeing more and more designs with the vias covered.  Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA?  Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process?  Expecting .001" but getting
.0007-.0008" copper plating.

Should via's be left uncovered?

Respectfully

Paul


--
Paul Truit, Mfg. Eng.
RBB Systems, Inc.
4265C E. Lincolnway
Wooster, OH  44691
Ph. (330) 567-2906 ext 514
Fax (330) 263-5324
Email: [log in to unmask]

---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------

ATOM RSS1 RSS2