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December 2001

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Subject:
From:
Andre Leclair <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 12 Dec 2001 07:25:59 -0600
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text/plain (18 lines)
Hi all
I hope this gets some good advice.

I have a customer who is requiring the placement of an electrolitic cap
that has a lead spacing of 0.140" and the PCB has 0.100".  They do not want
the leads formed, they want the part flat to the board.  In doing this, am
I opening myself up to stress induced failures of the component.

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