I have been asked to justify routing of traces beneath chip components.
Does anyone have a spec, standard or documentation defining what trace
widths should be allowed beneath what packages?
As always any help is appreciated and all comments are solicited.
Thanks in Advance
FNK
Frank N Kimmey, C.I.D.+
Senior PCB Designer
Powerwave Technologies
PH. 916-941-3159
Fax 916-941-3195
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