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October 2001

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Subject:
From:
"Mcmaster, Michael" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 26 Oct 2001 16:12:46 -0700
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I've approached this problem in the past by looking at a yield per layer.
Obviously a lot of assumptions have to be made in terms of density of
layers, complexity of circuits, size of board, number of holes, which layers
to include, etc.  But if you're trying to get an idea of what role the
number of layers plays on yields, I still think it's effective.

I usually make a little spreadsheet that keeps raising the yield per layer
to the appropriate power.  For instance if you're yield per layer is 99%,
the yield for 2 layers is 98%, for 3 it is 97%.  The equation looks linear
here but that's just because 0.99 is so close to 1 and you're looking at
only a few layers.  If you increase the number of layers and drop the yield,
you'll see the curve is actually asymptotic.

So let's look at your scenario.  For a 12-layer board, let's assume 6 signal
layers with a 93% yield.  Working backwards, I get a yield of 98.8% per
layer.  Applying this to a 24 layer board with 12 signal layers, the yield
should be 86.5% versus the 82% you are reporting.  Looks to me like you are
sandbagging it on the 24-layer board!  ;-)

Just kidding of course.  As I said the assumptions are critical, but I still
think this is a good way to show how the number of layers impacts yields.



> ----------
> From:         Hinners Hans M Civ
> WRALC/LUGE[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Thursday, October 25, 2001 8:44 AM
> To:   [log in to unmask]
> Subject:      [TN] Innerlayer shorts - predictions vs. reality
>
> Good Morning All!
>
> I think I've got a case of folks comparing apples to bananas.
>
> I'm trying to predict % defects due to inner layer shorts and compare
> across
> part numbers.  Folks are looking at one part number and saying, "12 layer
> board with 7% inner layer shorts (of the ones tested) and looking at
> another
> part number - 24 layer board has 18% inner layer shorts.  You are screwing
> up more on the big $$$ board - fix it!"  Shouldn't inner layer shorts be a
> linear or geometric relationship?
>
> For example, take a 10 layer board, it has 5 signal layers (50-50 signal &
> plane).  Each signal layer will have a certain surface area where traces
> are
> packed close enough together that a sliver of metal could cause a short.
> At
> electrical test I fail a certain percentage of boards due to shorts - say
> 10%.  Now take a 20 layer board and say it doubles the surface area that
> could have a short.  The failures due to inner layer shorts should be
> double
> the 10 layer board or 20%.  If the boards were manufactured at the same
> time
> the process should, on average, contribute the same number of shorts/area
> to
> each.
>
> Inner layer short defects come from multiple sources that produces a
> finely
> boned fish - metallic contamination, poor IL etching, poor IL
> imaging/development, missed in IL AOI, equipment, material, method, people
> -
> ad nausem. . . And for now I'm ignoring test escapes.  The inner layer
> short
> generation fluctuates over time but has some average value per area.  So I
> propose a simple equation:
>
> Inner Layer Defects = (average # inner layer shorts/surface area) (total
> critical surface area)
>
> Looking at the artwork should get me the critical surface area, the inner
> layer defects we know from Electrical Test so a graph of defects vs.
> surface
> area should get me the shorts/area for the total process, no?  Then I can
> say when the process has changed versus merely a higher tech board being
> processed.
>
> Anybody hit this wall before?  Is there a flaw in my logic?
>
> Hans
>
> PS.  If memory serves, I remember Bev mentioning Technetters' lack of
> gender
> identification skills at that "Stump the Chumps" session we had a few
> years
> ago.  And I can relate - every once in a while people see the middle name
> (Michel) and think "must be a groovy chick".
>
> Integrity First  -  Service Before Self  -  Excellence in All We Do
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> Special Operations Forces System Program Office (SOF - SPO)
> Gunship Team
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax:   (478) 926 - 4911
> DSN Prefix: 468
>
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