Thanks everyone for your input.  I'll think I'll just leave it up to the
fabricator to know what they're to do (they do, don't they?) and leave it
at that.  If they plate after solder mask, it would save precious metal
use, and maybe 'save us a buck or two.'

OH, by the way, on another subject...
Anyone out in TechNet land know of tech pubs or papers dealing with solving
or decreasing susceptability problems for CE testing?  We (I) have a board
design that is just barely passing the 3V/m test, and the same board in
another configuration fails the same test.  (oops)  Am I giving enough
information (you know, the dead brain cell thing...)?
I humbly await the collective wisdom of the scholars and gurus of
Technet...
Sincerely,
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]


Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511

---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send the following message: SET Technet NOMAIL
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------