Genny,

There is a visual way,  if your board has no more than 8 to 10 layers.
If room on one edge of board you create a layer window strip through the board.
Every layer has a void of copper (say 1 inch long) then every layer has its layer number
etched in the voided area.  Of course the numbers need to be staggered so you can
look through this window and read number order.  Example  1 2 3 4 5 6 7 8
This just doesn't work well if you start to get large layer count PWBs.

You might also want to look at how you are marking your gerber files.
We title every layer clearly (large text) with "layer #, purpose"
        LAYER 1- PADS ONLY, COMPONENT SIDE
        LAYER 2- GROUND PLANE A
        LAYER 3-SIGNAL 1
        LAYER 4- GROUND PLANE B
then follow up with a read file which creates the stackup order by  gerber file names vs PWB
layer.
    TOP.GBR = LAYER 1, COMPONENT SIDE
    GNDA.GBR = LAYER 2, GROUND SHIELD
    SIG1.GBR = LAYER 3, SIGNAL
    GNDB.GBR = LAYER 4, GROUND SHIELD
Also on fabrication drawing we create a stackup detail showing prepreg and core thickness
specifically designed for this PWB. (of course we consult our fabricator before hand)
Then each copper layer is named with the exact name we used to name the gerber file.

maybe a coupon could be created so when cross sectioned it would show correct order
was accomplished.  This coupon could be required for every order of fabrication.

This is a tough one and really hurts when this occurs.
Greg Scott
Cray Inc.
Sr. Designer

Genny Gibbard wrote:

> Good morning,
> My morning has not been so good.  I have a build of PCB's (over 300 boards)
> where two inner layers have been swapped.  The board fabricator constructed
> the board in the wrong order.  These boards are RF in nature and have
> frequencies approaching 2GHz on them.  In many places we put a signal trace
> on the inner layer furthest from the component side and then a wide grounded
> trace over it on the closer inner layer as shielding.  So not only is there
> no longer shielding over many traces, these signals are also about .03"
> closer to the component circuitry than they used to be.  Can you contemplate
> the nightmare of spurious issues that have been created?  We did not notice
> the problem until they were fully populated and almost thru our testing
> process and started failing one of the tests miserably.
> Needless to say, we will be revising our inspection techniques to try to
> catch occurrences like this much sooner.
>
> I was wondering if anyone knows of a way that layer order could be
> electrically tested for on a bare board, that we could require our
> fabricator to complete?
>
> Genny Gibbard (mailto:[log in to unmask])
>
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