Hi Hans,
You do not seem to account for spacing within the surface being looked at.
There is a substantial difference between boards with 10 mil spacing between
conductor traces and those with say 4 mils.
Another potential flaw is the length that traces run close to each other.
Even if 2 boards are allowed and use 5 mil spacing, if one uses it on 10% of
the layer and the other on only 2% you will get different yields.
My opinion only.
Have a nice day,
Alain Savard
QA-PCB
CAE Inc.
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 11:44 AM
To: [log in to unmask]
Subject: [TN] Innerlayer shorts - predictions vs. reality
Good Morning All!
I think I've got a case of folks comparing apples to bananas.
I'm trying to predict % defects due to inner layer shorts and compare across
part numbers. Folks are looking at one part number and saying, "12 layer
board with 7% inner layer shorts (of the ones tested) and looking at another
part number - 24 layer board has 18% inner layer shorts. You are screwing
up more on the big $$$ board - fix it!" Shouldn't inner layer shorts be a
linear or geometric relationship?
For example, take a 10 layer board, it has 5 signal layers (50-50 signal &
plane). Each signal layer will have a certain surface area where traces are
packed close enough together that a sliver of metal could cause a short. At
electrical test I fail a certain percentage of boards due to shorts - say
10%. Now take a 20 layer board and say it doubles the surface area that
could have a short. The failures due to inner layer shorts should be double
the 10 layer board or 20%. If the boards were manufactured at the same time
the process should, on average, contribute the same number of shorts/area to
each.
Inner layer short defects come from multiple sources that produces a finely
boned fish - metallic contamination, poor IL etching, poor IL
imaging/development, missed in IL AOI, equipment, material, method, people -
ad nausem. . . And for now I'm ignoring test escapes. The inner layer short
generation fluctuates over time but has some average value per area. So I
propose a simple equation:
Inner Layer Defects = (average # inner layer shorts/surface area) (total
critical surface area)
Looking at the artwork should get me the critical surface area, the inner
layer defects we know from Electrical Test so a graph of defects vs. surface
area should get me the shorts/area for the total process, no? Then I can
say when the process has changed versus merely a higher tech board being
processed.
Anybody hit this wall before? Is there a flaw in my logic?
Hans
PS. If memory serves, I remember Bev mentioning Technetters' lack of gender
identification skills at that "Stump the Chumps" session we had a few years
ago. And I can relate - every once in a while people see the middle name
(Michel) and think "must be a groovy chick".
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
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