Hi, Rob,
I would have a look into pad sizes and footprints relative to the package
types in question. If they're too long for the contact length of the IC
pins and/or the footprint is too large (i.e. the pads start too far away
from the component body centre), the toe joint will be deficient of solder,
as the excessive pad area act as a solder thief. Conversely if the pad is
too short and/or the footprint is too small, the toe joint will also
deviate from the ideal.
I have had my own headaches recently with designers and routers not being
confident about how to define pad sizes on boards. The standard answer has
been "if there is a land pattern specified in the component data sheet for
a specific component, use that land pattern. If no land pattern is
specified, but the package type carries a JEDEC package number or RLP
(registered land pattern) number, then you can look up land patterns in
IPC-SM-782. Failing that, calculate them for yourself - so much for
international standards!
With apologies to Rob for usurping his question, I have a point and
supplementary question of my own to ask you good folks. My recent problem
is that IPC-SM-782 is not written around JEDEC package numbers, but more
around RLP numbers. Except in a very few instances, there is no
correlation/cross-reference between JEDEC nos and RLP nos in SM-782, and
precious few data sheets state the RLP number for the parts they cover.
It's more common to find JEDEC numbers in the data sheets, but even those
are in the minority among the large bundle of data sheets that document all
the components used on a board and most of them cannot be found in SM-782.
Mostly data sheets just give the package style (PLCC68, QFP160, etc) and
its dimensions, which can be looked up in SM-782, although when it comes to
TSSOP's and SSOIC's, SM-782 is no use whatsoever, as it doesn't cover them.
More often than not, you have to calculate your own pad sizes, because
manufacturers have their own variations on the standard component package
theme instead of sticking to a standard and making life a lot easier for
everyone. Pad size calculation can be done using formulae given in SM-782,
or there are calculators available either on-line on from the IPC site
where you plug in component dimensions and it gives you a land pattern in
return. We compared results using a very rare component - one that had a
land pattern in the data sheet AND whose JEDEC number was covered by SM-782
- between datasheet-specified land pattern, land pattern given in SM-782,
and calculation using SM-782 formulae and an IPC compatible calculator
taken from the Net. We found none of the results were very close to each
other, so we were at a loss as to which to choose.
There is a table 3-4 in SM-782, headed Chip Components, that gives solder
joint dimensions that the text in the spec says are applicable to all
electronic components. However, many data sheets beg to differ, so the
table is unreliable, and there's no other comparable information elsewhere
in SM-782.
My question (at last) is this: When you have to calculate your own pad
sizes for different components, most of the parameters required can be
lifted out of the data sheets, but how do you determine, or from where do
you obtain, the allowance needed for the heel and toe solder joints? They
differ considerably from one component type to another, judging by other
data sheet information, so I don't want to just use SM-782's universal
table, which seems to err on the stingey side anyway. What I thought would
be a science is still an art it seems. Can any of you wizards at board
design / layout / manufacture give a definitive answer on pad size
calculation? What parameters need to be considered when determining pad
sizes, apart from soldering process to be used?
Rob, Good luck with improving your joints and apologies again for
comandeering your question to raise one of my own.
TVMIA
Peter Duncan
Rob Day
<[log in to unmask] To: [log in to unmask]
COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] solder reflow question
<[log in to unmask]
ORG>
09/26/01
08:08 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello folks,
We have a problem with some IC's and solder quality on a board that we are
running. The inspector told me we had problems with the toe solder joints.
The reflow throughout the rest of the board looks pretty good. This solder
problem around the IC is not a consistent one. The solder is not
rejectable, but we would like it to look better.
I have tested our profile with some profiling tools and the profile is very
good. Our paste is only 1 day old. Could it be some of the pads on the
raw board?
Is there anything else that you folks would check as part of a typical
problem solving approach as I am relatively new to the industry.
Your comments would be greatly appreciated.
Thanks,
rob day
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