Tim, I agree with Mike.
While vertical stacking MIGHT be OK for resistor chips, it's dangerous for
ceramic chip capacitors. There's a danger of creating internal cracks in
capacitor chips, and these might not be detected during ICT or functional
testing, since the initial insulation resistance of the cracked chip may be
too high for reliable detection during circuit testing. But such cracks
may worsen with time, temperature, humidity, and voltage cycling, and can
result in leakage or short circuit failures later.
Dick
Mike Di Giacomo <[log in to unmask]>@IPC.ORG> on 09/26/2001
11:07:51 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] SMD chip stacking
Tim,
If you're absolutely sure that the product with the stacked chips
isn't going to being used for any purpose other than for a bench test then
okay. Otherwise I don't recommend it. In my experience the solder joints on
stacked components are poor and there is no obvious way of knowing what
damage was done to the components.
Hope this helps,
Mike Di Giacomo
Process Development Engineer
-----Original Message-----
From: Tim Devaul [mailto:[log in to unmask]]
Sent: Wednesday, September 26, 2001 10:11 AM
To: [log in to unmask]
Subject: [TN] SMD chip stacking
Good morning,
I am in the middle of a slight disagreement between a couple of our
company's organizations. It is over stacking
SMD chips, specifically 0603s. In a temporary rework fix engineering wants
to stack and solder one chip directly on top of the other. Does anyone have
any experience positive or negative concerning this practice?
Tim DeVaul
Quality Assurance Training and Audit Supervisor
Philips Broadband Networks, Inc.
100 Fairgrounds Dr.
Manlius, New York 13104
Tel: (315) 682-9105 Ext. 2403
Fax: (315)682-9006
Email: [log in to unmask]
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