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September 2001

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Subject:
From:
Jack Crawford <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 19 Sep 2001 12:01:03 -0500
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>>> "Stewart, Dougal" <[log in to unmask]> 09/19/01 11:35AM >>>

check out Interconnect stress testing as provided by Bill Birch in Canada.
For reliability testing this not only provides good data on build/drill A
versus B, but identifies where the weaknesses are.

Dougal Stewart
Director of Technology Development, 
Viasystems Europe
tel:   +44 191 206 2081
mob:+44 780 221 1958


-----Original Message-----
From: Jack Crawford [mailto:[log in to unmask]] 
Sent: 18 September 2001 18:17
To: [log in to unmask] 
Subject: Re: [TN] Via Reliability and Thermal Shock


>>> "Buscomb, Scott" <[log in to unmask]> 09/18/01 11:10AM >>>

I am looking for research on via reliability under thermal shock. I am
particularly interested in drilled via (>200um). Is anyone aware of any
papers, studies, etc?
Thanks in advance,

Scott Buscomb
PCB Design Engineer
Zight Corporation
www.zight.com 

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