Hi Ken,

Here's a few things that I remember from a previous job:

Because the via's will fill-up with solder from the solderpaste, you need to compensate the stencilopenings so that there will still be enough solder to form a good joint. The amount of compensation should be roughly twice the volume of the via. You'll probably have to print beyond the edges of the pads.
Besides larger opening, this could also mean that you need a thicker stencil. The 250  micron stencils that we used were not compatible with fine-pitch components. This forced us to use step-etched stencils whenever there was fine-pitch on the board.
When double sided reflow, you could have some troubles with the solder that protrudes from the via's after the first soldering step, which prevents the stencil from laying flat on the board. For this reason we made an extra opening in the 2nd-side stencil for every via-in-pad. 
Last problem that I remember is that relatively large amounts of flux residues are concentrated at the bottom of these via's, excactly where we needed to probe for the incircuit test. Since we didn't clean the boards this was our most serious problem. 

Lots of challenges for you ! 

Best regards,

Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net

>>> Ken Patel <[log in to unmask]> 08/08 8:52 pm >>>
Assemblers,
How robust is the VIA in the pad technology now? Can someone share the
process of handling board that has vias in pads?

Most of our boards have VIAS in the pads and there is no way out.

re,
Ken Patel

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