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August 2001

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Subject:
From:
Richard Hamilton <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 31 Aug 2001 14:16:43 -0700
Content-Type:
text/plain
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Peter,

Based on a past life:

I am not sure what is failing. I have always been under the impression that
the Hi Pot test was to test the primary incoming wires of the device to any
'accessable' metal cabinetry or case. Can I assume your boards are in this
'line of fire'?

We had a no clean process but our boards were not in the 'path' as I noted
above. Now, this is based on UL requirements, you may be testing for
something else.

My experience does not indicate any connection between the no clean flux
left on the board and any continunity to anything so my general comment is,
no problem.

Maybe if you can give me a little more indication of what you are actually
testing I might be able to give another 2 cents worth!?

Good Luck

Richard

At 10:47 AM 8/31/01 -0700, you wrote:
>Hello,
>
>Does anyone have experience in determining the root causes for hi-pot
>test failures?
>
>I am especially interested in the effect of flux residues remaining from
>no-clean hand soldering. The DUTs are being screened with a 3KV, 10sec
>hi-pot tester. So far my results are inconclusive as to whether the flux
>seen on the board has any influence on the test results.
>
>
>Rgds,
>Peter
>

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