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August 2001

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Subject:
From:
Neil Atkinson <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 16 Aug 2001 17:56:48 +0100
Content-Type:
text/plain
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text/plain (243 lines)
We found that the thief pads or and enlarged final pad work reasonably well
but in a small amount of cases the enlarged pad fails to prevent a bridge
and that the bridge doesn't always take to a separate thief pad.

By connecting the thief pad to the last pad it seems to encourage the bridge
to take place whilst thieving a consistently larger amount of solder that a
large final pad.  It is so effective that it results in a very lean (for a
wave soldered board) joint on the final leg of the IC and I have NEVER seen
a bridge on the last two legs with this layout.

I don't have any theory on this layout, it was a spin off from a different
project when I was trying to drain a pad to be as flat as possible after
wave soldering.  If anyone else tries it, let me know.

We simply connect the thief pad to the last pad by a fine track between the
centre of the pads give it a go and let me know.

If anyone would like to apply some theory to this I would be interested!!

Neil


Neil Atkinson - Quality Manager
Stadium Electronic Controls Division
Stephen House, Brenda Road, Hartlepool TS25 2BQ



                -----Original Message-----
                From:   Gerry Savard [mailto:[log in to unmask]]
                Sent:   16 August 2001 14:45
                Subject:        Re: Wavesoldering SOIC's

                Hi Neil,
                    I've never heard of connecting the thief pads with a
track, can you give
                us a little more detail as to location (centered on pads, at
the end of
                pad?).  What's your theory on what the track does?

                Thanks
                Gerry


                ----- Original Message -----
                From: Neil Atkinson <[log in to unmask]>
                To: <[log in to unmask]>
                Sent: Wednesday, August 15, 2001 8:47 AM
                Subject: Re: [TN] Wavesoldering SOIC's


                > Try a pad layout with thief pads connected to the last two
pads by a very
                > fine track.
                >
                > We developed this layout during a six sigma project and
found it better
                than
                > anything else.
                >
                > Does anyone else out there use this method - or should I
have patented it
                > before giving my secrets away??
                >
                > Random bridges elsewhere sound to me like a process
problem - perhaps you
                > need to do more @measuring and analysing' to determine the
real KPIV's
                > before putting all your money on layout.
                >
                > I have carried out a few six sigma project on wave
soldering so please
                stay
                > in touch on how you get on.
                >
                > A good starting point is a good Ishikawa diagram
(attached).
                >
                > Neil
                > Neil Atkinson - Quality Manager
                > Stadium Electronic Controls Division
                > Stephen House, Brenda Road, Hartlepool TS25 2BQ (UK)
                >
                >  <<CED ws.ppt>>
                >
                >                 -----Original Message-----
                >                 From:   Adrian Irwin
[mailto:[log in to unmask]]
                >                 Sent:   14 August 2001 12:10
                >                 Subject:        Wavesoldering SOIC's
                >
                >                 I am currently involved in Black Belt
project which has
                > focussed on
                >                 Wavesolder defects. We wave 0805 SMT
assemblies and the
                > majority of the
                >                 defects are shorts on SOIC's.
Approximately 50% of the
                > solder shorts are on
                >                 the back 2 pins, with the remaining shorts
being
                distributed
                > randomly
                >                 across the other pins. We do not use thief
pads but have
                > elongated the pad.
                >                 The current size is 0.5mm / 2mm.
                >
                >
                >                 Do we realy need thief pads because as we
are seeing 50%
                of
                > the solder
                >                 shorts distributed randomly across all
other pins? and is
                it
                > possible to
                >                 achieve sub 50 ppm (DPMO) for SOIC's?
                >
                >                 Has anybody tried using a pad design that
increments in
                > length as they
                >                 progress to the back pins? I am looking to
set up a test
                pcb
                > that will
                >                 optimise the pad design, any suggestions
on other pad
                > shapes.
                >
                >                 Any help on this problem would be greatly
received.
                >
                >

############################################################################
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                >
                > Thank You - Stadium Group Plc., IT Department - Tel: +44
(0)1429 266544
                >

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#####################################################################################
Attention:

This message is for the named person's use only.  It may contain confidential,
proprietary or legally privileged information.  No confidentiality or privilege
is waived or lost by any mistransmission.  If you receive this message in error,
please immediately delete it and all copies of it from your system, destroy any
hard copies of it securely and notify the sender.  You must not, directly or
indirectly, use, disclose, distribute, print, or copy any part of this message
if you are not the intended recipient. STADIUM GROUP PLC and any of its subsidiaries
each reserve the right to monitor all e-mail communications through its networks.
Any views expressed in this message are those of the individual sender, except where
the message states otherwise and the sender is authorised to state them to be the
views of Stadium Group Plc. or one of its subsidiaries.

Although this message has been scanned by MailMarshall for known viruses and
inappropriate content, we recommend that recipients employ appropriate measures on
their systems to intercept any such material.

Thank You - Stadium Group Plc., IT Department - Tel: +44 (0)1429 266544
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