Hi Neil,
I've never heard of connecting the thief pads with a track, can you give
us a little more detail as to location (centered on pads, at the end of
pad?). What's your theory on what the track does?
Thanks
Gerry
----- Original Message -----
From: Neil Atkinson <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, August 15, 2001 8:47 AM
Subject: Re: [TN] Wavesoldering SOIC's
> Try a pad layout with thief pads connected to the last two pads by a very
> fine track.
>
> We developed this layout during a six sigma project and found it better
than
> anything else.
>
> Does anyone else out there use this method - or should I have patented it
> before giving my secrets away??
>
> Random bridges elsewhere sound to me like a process problem - perhaps you
> need to do more @measuring and analysing' to determine the real KPIV's
> before putting all your money on layout.
>
> I have carried out a few six sigma project on wave soldering so please
stay
> in touch on how you get on.
>
> A good starting point is a good Ishikawa diagram (attached).
>
> Neil
> Neil Atkinson - Quality Manager
> Stadium Electronic Controls Division
> Stephen House, Brenda Road, Hartlepool TS25 2BQ (UK)
>
> <<CED ws.ppt>>
>
> -----Original Message-----
> From: Adrian Irwin [mailto:[log in to unmask]]
> Sent: 14 August 2001 12:10
> Subject: Wavesoldering SOIC's
>
> I am currently involved in Black Belt project which has
> focussed on
> Wavesolder defects. We wave 0805 SMT assemblies and the
> majority of the
> defects are shorts on SOIC's. Approximately 50% of the
> solder shorts are on
> the back 2 pins, with the remaining shorts being
distributed
> randomly
> across the other pins. We do not use thief pads but have
> elongated the pad.
> The current size is 0.5mm / 2mm.
>
>
> Do we realy need thief pads because as we are seeing 50%
of
> the solder
> shorts distributed randomly across all other pins? and is
it
> possible to
> achieve sub 50 ppm (DPMO) for SOIC's?
>
> Has anybody tried using a pad design that increments in
> length as they
> progress to the back pins? I am looking to set up a test
pcb
> that will
> optimise the pad design, any suggestions on other pad
> shapes.
>
> Any help on this problem would be greatly received.
>
>
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