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July 2001

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From:
Steve Kingdon <[log in to unmask]>
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Date:
Tue, 31 Jul 2001 16:59:56 +1200
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Good morning,

We are currently developing a card which has high aspect ratio, through
hole vias. Out of necessity (fine pitch bgas) we have had to use a number
of 10 mil FHS holes in four localised areas, the rest of the via holes we
have specified at 12 mil FHS. The card is 15" x 12", FR4, 12 layers and 93
mil thick. We did the right thing and talked to both our prototype fab
house and mass production fab house, and they say they can manufacture
these cards using this via technology.

During assembly of the prototypes, a component had to be reworked. At our
hardware lab, the engineer that is debugging the board believes that
several vias under the reworked component are open circuit. We have
assumed that the thermal excursion during the rework process caused the
via barrel to crack, as the rest of the pcb appears to operate correctly.
The vias that failed were 12 mil vias. The boards were bare board
electrically tested.

We did not specify the Tg of the FR4 material, but upon approaching our
prototype vendor, were told that the Tg of the material used was 155 deg C.

My feeling is that we need to qualify this via technology before it is put
into mass production, but I am having trouble finding resources.

My questions are:

1. To qualify this via technology I am thinking that we could microsection
a via to check plating thickness. What other things can be checked during
a microsection? Also we could thermally cycle a board to simulate
operational conditions. I am guessing that we could either use true
operational cycle temperatures and number of cycles, or some kind of
accelerated lifetime testing. I am looking for papers and standards on
this topic. Can one include assembly process and rework temperature
excursions into the themal cycling? Are there any other via reliability
tests that can be done?

2. I understand the stress endured by a via barrel is proportional to the
force applied to the via barrel and cross sectional area of the barrel
that must support the force. There must be a standard for minimum plating
thickness, but am having trouble finding it. We specified plating up from
1/2 oz to 1 oz, so would assume we would get 1/2 oz in the barrel. Are
there any papers out there that detail what happens to a multilayer PCB
via during z axis expansion of the laminate.

3. When does one specify high Tg materials? Is there a cut off point
determined by board thickness? Or should we be specifying 170 deg C FR4 or
another low CTE material just to be on the safe side?

4. How do you know at what point to go to another via technology eg. blind
and/or buried vias, for PCB manufacturing reasons alone, We are not
looking at this kind of technology at the moment for density reasons, but
I can see that by using B/B vias that the aspect ratio is not a problem
any more. Is this a correct assumption?


Thanks in advance.

Steve.













-------------------------------------------------------------
Steve Kingdon            27 Nazareth Avenue
PCB Layout Engineer      PO Box 8011
Allied Telesyn Research  Christchurch
phone +64 3 339 9224     New Zealand
fax   +64 3 339 3002     email: [log in to unmask]
                         web: http://www.alliedtelesyn.co.nz/
-------------------------------------------------------------

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